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I'm finishing up a PCB layout which contains a 6.5 GHz ultra-wideband transceiver with a chip antenna, an ARM controller running at 72 MHz with a 12 MHz crystal, a 16 MHz SPI bus with 3 peripheral components, USB communications, and a buck converter.

Handling the EMI and decoupling considerations has been a real learning experience :) I've used good design practices, as I understand them. I have only one more question before shipping off this design.

I am generally placing decoupling caps like so (this is an 0402 cap):

decouple

The vias are going to internal ground and power planes.

For additional shielding, I want to do a selective flood fill on the top and bottom layers of the (4-layer) PCB and stitch them to the ground plane. I wasn't planning to allow this fill to connect to the pads of the decoupling caps.

My question: should I allow thermals to connect to the ground vias, even though the decoupling should already be sufficient? Or is it preferred to keep them isolated? Here is an example of connecting the vias to the top fill:

decouple2

Thanks!

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  • \$\begingroup\$ Just curious, what program is this made in? It looks really nice, almost like Altium Designer. \$\endgroup\$
    – Funkyguy
    Commented Jul 10, 2014 at 16:31
  • \$\begingroup\$ @ShannonStrutz It's the current version (16.6) of Cadence (OrCAD) PCB Editor. I'm still learning some of the basics. It's a powerful software, but it's surprisingly non-intuitive :) \$\endgroup\$
    – bitsmack
    Commented Jul 10, 2014 at 16:51
  • \$\begingroup\$ Whoa! I did not know they offered a free version. This is going on the list of things to learn. \$\endgroup\$
    – Funkyguy
    Commented Jul 10, 2014 at 16:57
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    \$\begingroup\$ @ShannonStrutz I don't know anything about the free version; my company has the basic license which includes OrCAD Capture and PCB Editor. But if they have one, then I say go for it! It's a good program to know :) Seems pretty popular in industry. I warn you, it has a really steep learning curve. I highly recommend the book Complete PCB Design Using OrCAD Capture and PCB Editor by Kraig Mitzner. It's been invaluable. \$\endgroup\$
    – bitsmack
    Commented Jul 10, 2014 at 17:08
  • \$\begingroup\$ Would using selective flooding really improve shielding? I mean, the field lines are going through the inner GND layer anyway aren't they? I wonder if it is considered a good practice for most designs? \$\endgroup\$
    – Rev
    Commented Aug 10, 2014 at 16:22

2 Answers 2

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I suppose it depends on what you want to use the selective fill for. Is it supposed to be just a shielding? Is it going to be large enough to be considered it's own ground plane?

In the former case, I'd guess at 'no', but in the latter case, sure. The truth is that it may not matter anyway, especially if the stitching is done well.

One thing I see that may cause an issue is how close the vias are to the component pads. For some assemblers I suppose this isn't a problem, but the one I use wants to see 10mils (10 thousandths of an inch) between the edge of the pad and the via. This helps with solderability and solder-stealing issues.

If you're really stressing about the EMI, you might consider using X2Y capacitors for bypassing, making sure to follow their layout guidelines (6 vias per component)

http://www.johansondielectrics.com/x2y-products.html

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    \$\begingroup\$ I agree about the via spacing. Minimum annular ring sizes are typically set to allow the hole to break out ouf the pad by something like 25% due to misregistration. If that happens in this case, the hole could end up practically in the middle of the SMT pad. \$\endgroup\$
    – The Photon
    Commented Jul 7, 2014 at 20:22
  • \$\begingroup\$ I wasn't aware of those four-pad-X2Y capacitors. Sounds interesting but also like a marketing thing. Does anyone have some practical experience with those? Are they really such an improvement over conventional decoupling / filtering with MLCC? \$\endgroup\$
    – Rev
    Commented Aug 10, 2014 at 16:13
  • \$\begingroup\$ I've used them in a design, under a Cyclone IV FPGA in a tight 4-layer layout. The specs characterize it with a much lower self-inductance figure which improves the decoulping performance. I don't have the tools to verify this behavior, but I don't have any reason to doubt it either. \$\endgroup\$
    – Daniel
    Commented Aug 11, 2014 at 17:16
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Even if you flood your top layer rarely it is going to work as a ground plane. There will be a lot of gaps in it.

So if you consider your ground plane is layer 2 make a good connection (=low inductance connection) to it through a via (or two!)

Why don´t you consider add another via to each decooupling capacitor pad and make wider its connection?

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