I'm creating an ALU in Verilog, and I would like overflow to be dealt with by wrapping around to lower values.
For example:
0000_0001 + ffff_ffff == 0000_0001
0000_0011 + ffff_ffff == 0000_0011
0000_0012 + ffff_fffe == 0000_0011
Is it possible to achieve this in Verilog?
0000_0001 + ffff_ffff
to be0000_0001
and not0000_0000
(which is what you'd get in typical integer arithmetic on a computer)? What result do you want forffff_ffff + 0000_0000
? \$\endgroup\$