Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog

Question

I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input to the SRLC32E and coefficient value form coefficient memory but don't get actual output.

The reason is that I don't have the right clarity about how my input data and coefficient value will synchronize at the same edge and give me the correct result after some clock cycle.

timescale 1ns / 1ps

module filter_dsp8(
input clk,rst,ce,inp_valid,
input signed [17:0]data_in,
output reg out_valid,
output reg signed [47:0]out=0
);
reg signed [17:0]h1,h2,h3,h4,h5,h6,h7,h8;
reg out_valid_tmp;

reg  [17:0]coef[0:7];// coef is a memory element

reg signed [4:0]ADDR0=0,ADDR1=0,ADDR2=0,ADDR3=0,ADDR4=0,ADDR5=0,ADDR6=0,ADDR7=0;
//wire [29:0]coef_extend;
//wire signed [17:0]data_srl_in=0;
wire signed[17:0]data_srl_out;
wire signed[47:0]PCOUT_0, PCOUT_1, PCOUT_2, PCOUT_3, PCOUT_4, PCOUT_5, PCOUT_6, PCOUT_7;//for dsp
reg [8:0] OPMODE=0;
wire signed [47:0]POUT_TMP;
reg signed [47:0]out_tmp=0;

//integer i;

//assign  coef_extend={{12{coef[17]}},coef[i]};
 
initial begin
    coef[0]=18'd1;
    coef[1]=18'd2;
    coef[2]=18'd3;
    coef[3]=18'd4;
    coef[4]=18'd5;
    coef[5]=18'd6;
    coef[6]=18'd7;
    coef[7]=18'd8;
end  

always@(posedge clk)begin
       if(rst)begin
           ADDR0<=0;
           ADDR1=0;
           ADDR2=0;
           ADDR3=0;
           ADDR4=0;
           ADDR5=0;
           ADDR6=0;
           ADDR7=0;
        end            
       else begin
        ADDR0<=ADDR0+1;
        ADDR1<=ADDR0;
        ADDR2<=ADDR1;
        ADDR3<=ADDR2;
        ADDR4<=ADDR3; 
        ADDR5<=ADDR4;
        ADDR6<=ADDR5;
        ADDR7<=ADDR6;
       end
end

always@(posedge clk)begin

       if(rst)begin
        h1<=0;h2<=0;h3<=0;h4<=0;h5<=0;h6<=0;h7<=0;h8<=0;   
        end            
       else begin
       
       h1<=coef[ADDR0];
       h2<=coef[ADDR1];
       h3<=coef[ADDR2];
       h4<=coef[ADDR3];
       h5<=coef[ADDR4];
       h6<=coef[ADDR5];
       h7<=coef[ADDR6];
       h8<=coef[ADDR7];

       end
end

always@(posedge clk)begin
      if(rst)begin
      OPMODE<=0;
      end
      else begin
      OPMODE<=9'b000010010;
      end           
end
/*always@(posedge clk)begin
      if(rst)begin
          out_tmp<=0;
          out_valid_tmp<=0;
      end                      
      else begin
       
          out_tmp<=POUT_TMP;
          out_valid_tmp<=1;
          out<=out_tmp;
          out_valid<=1;
      end                 
end
  
*/
always@(posedge clk)begin
      if(rst)begin
         out_tmp<=0;
         out_valid_tmp<=0;
      end 
      else begin
         if (ADDR0==5'd0)begin
           out_tmp<=POUT_TMP;
           out_valid_tmp<=1;
         end
       
          else if (ADDR0==5'd7)begin
            out<=out_tmp;
            out_valid<=1;
          end
          else begin
            out_valid<=0;
            out_valid_tmp<=0;
          end   
       end
end        

srl_32 s1 (.CLK(clk), .CE(ce), .A(5'd0), .D(data_in),  .Q(data_srl_out), .Q31());

DSP48_inst D1(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h1[17]}},h1}),   .B(data_srl_out), .C(48'd0),  .PCIN(48'd0),     .PCOUT(),   .P(PCOUT_0),     .ALUMODE(4'b0000),     .INMODE(5'b00000),   .OPMODE(9'b00_000_0101));
DSP48_inst D2(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h2[17]}},h2}),   .B(data_srl_out), .C(48'd0),  .PCIN(PCOUT_0),   .PCOUT(PCOUT_1),   .P(),     .ALUMODE(4'b0000),      .INMODE(5'b00000),   .OPMODE(9'b000010101));
DSP48_inst D3(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h3[17]}},h3}),   .B(data_srl_out), .C(48'd0),  .PCIN(PCOUT_1),   .PCOUT(PCOUT_2),   .P(),    .ALUMODE(4'b0000),      .INMODE(5'b00000),   .OPMODE(9'b000010101));
DSP48_inst D4(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h4[17]}},h4}),   .B(data_srl_out),.C(48'd0),   .PCIN(PCOUT_2),   .PCOUT(PCOUT_3),   .P(),    .ALUMODE(4'b0000),     .INMODE(5'b00000),   .OPMODE(9'b000010101));
DSP48_inst D5(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h5[17]}},h5}),   .B(data_srl_out), .C(48'd0),  .PCIN(PCOUT_3),   .PCOUT(PCOUT_4),   .P(),    .ALUMODE(4'b0000),      .INMODE(5'b00000),   .OPMODE(9'b000010101));
DSP48_inst D6(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h6[17]}},h6}),   .B(data_srl_out), .C(48'd0),  .PCIN(PCOUT_4),   .PCOUT(PCOUT_5),   .P(),   .ALUMODE(4'b0000),      .INMODE(5'b00000),   .OPMODE(9'b000010101));
DSP48_inst D7(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h7[17]}},h7}),   .B(data_srl_out),.C(48'd0),   .PCIN(PCOUT_5),   .PCOUT(PCOUT_6),   .P(),    .ALUMODE(4'b0000),      .INMODE(5'b00000),   .OPMODE(9'b000010101));
DSP48_inst D8(  .CLK(clk),   .RST(rst),   .CE(ce),   .A({{12{h8[17]}},h8}),   .B(data_srl_out), .C(48'd0),  .PCIN(PCOUT_6),   .PCOUT(),          .P(POUT_TMP), .ALUMODE(4'b0000),      .INMODE(5'b00000),   .OPMODE(9'b000010101));

/*srl_32 s2 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());
srl_32 s3 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());
srl_32 s4 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());
srl_32 s5 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());
srl_32 s6 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());
srl_32 s7 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());
srl_32 s8 (.CLK(clk), .CE(ce), .A(5'd24), .D(data_srl_in),  .Q(data_in), .Q31());*/

endmodule

Answer 1

This just needs attention to detail.

Use a sheet of squared graph paper, and trace, clock cycle by clock cycle, where every coefficient and datum is in their pipelines.

Alternatively, simplify your filter down to one non-zero coefficient, and your data down to a single non-zero datum, and fire them into your filter with different offsets. This simplifies the output, and allows the machine to tell you what the delays through the pipelines are.