I am using a Nexys A750T FPGA dev board and I would like to use the onboard DDR2 SDRAM. When I attempt to generate the MIG 7 series IP via the IP catalog, the IP wizard forces the design to be in VHDL (the target language for the project is VHDL) but I am unable to add the module to any block design (the option is greyed out when I right click the module, and the moduke is hidden when I go to add a module to a block design). If I create the IP via the block design system, the wizard forces the design to be in Verilog and forces the AXI interface to be enabled. I do not need the AXI interface for my purposes though. Is there some way to fix this other than possibly a full reinstall of Vivado?
1 Answer
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AXI4 is only available in verilog mode. And when you instantite MIG in IP Itegrator (IPI), AXI4 is by default enabled. And user cannot disable it. So you are forced to use verilog when using MIG in IPI. Now here is why:
Xilinx made a deliberate choice regarding this sort of design approach because IP Integrator primarily relies on AXI interfaces. IP Integrator simplifies the process of connecting IP components with AXI interfaces and a few additional signals. However, it's not meant to facilitate the graphical connection of other intricate interfaces. IP Integrator is specifically designed to graphically link AXI interfaces or individual ports. When incorporating the Memory Interface Generator (MIG), the AXI interface is automatically included for convenience, assuming that it will be connected to another component within IP Integrator.
If you utilize the IP Catalog outside of IP Integrator, it generates the necessary sources and instantiation templates. You then manually add the instantiation to your text-based RTL, allowing you the flexibility to connect it as desired.
So, why would one want a native mode interface in IP Integrator? Using it would require defining matching ports on a custom IP Integrator module and then connecting the individual ports between the two instances within IP Integrator. However, this contradicts IP Integrator's philosophy of simplifying the connection of various modules with predefined interfaces.
If Xilinx were to introduce other modules that could directly connect to the native interface of the Memory Interface Generator, they would likely incorporate support for it in IP Integrator.
But I still think Xilinx should leave it up to the users to decide what would be convenient for them. But for now you are stuck with it.
Here is a quick thing that you can try, that worked for me when I was working on another IP like this. You can instantiate the MIG from IP catalog into the test based RTL and create a top wrapper for it in VHDL. Then package you entire project as a new IP. Then create a new block design in a new vivado project and Instantiate this new IP in the block desgin. Hopefully it will be allowed by the vivado.
