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I am new to VHDL and am targeting a Spartan-7 FPGA, using VHDL. For technical reasons I have to develop outside the Vivado or other environments. It seems like there are several posts that have similar questions, like here and here. The first one I can't quite understand and the second one seems to increase the clock frequency and use Verilog rather than VHDL.

I found this post but it seems that it is more of a practice exercise. Implementing it was hard to get right and the resulting clock, when it worked, looked imprecise and sort of jagged on the scope.

I also understand from various posts that there is something called a PLL (phase-locked loop) that will help and it is natively implemented on each chip with correspondingly chip-dependent VHDL implementations. I don't really understand how to find the documentation for PLL or if it's something I can access via "pure" VHDL, that is, not in an environment like Vivado.

So, the question boils down to: How can I get a reliable 80 MHz clock from a 100 MHz clock input on the Spartan-7 chip without using Vivado or some similar proprietary environment? Perhaps a sub-question is: How do I implement a PLL on Spartan-7 with pure VHDL?

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    \$\begingroup\$ You cannot. The PLL is hardware specific to the FPGA and therefore requires specific instructions outside of pure VHDL. Since clocking in general can't be reliably routed through generic logic, that means it is all hardware specific which means you need external ICs to adapt your clock signal. The only other, rather unreasonable alternative, is to reverse engineer how the the Spartan's bit stream works. This will let you do whatever you want outside of the designated development environment but obviously won't be pure VHDL. \$\endgroup\$
    – DKNguyen
    Commented Mar 21 at 22:09
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    \$\begingroup\$ You say you're working outside of ISE/Vivado, but does the tool chain you're using provide access to all the hardware primitives, including the DCMs and PLLs? If so, the documentation on how to use the primitives directly is very much available, but it is somewhat of a steep learning curve. I can help with that, but I need to better understand exactly what your constraints are. \$\endgroup\$
    – Dave Tweed
    Commented Mar 22 at 0:29
  • \$\begingroup\$ I really wonder very much how do you plan to map and route the FPGA without their native tools? And yes, Spartan-7 does have dedicated tiles called "CMT", "Clock Management Tile", which let developers generate pretty much ANY clock. It contains all sort of multipliers for PLL and dividers, all with properly adjusted ranges for VCOs. Also the Xilinx tools have been under development by hundreds of fine engineers over many years, so your idea to bypass this process sounds blatantly implausible. \$\endgroup\$
    – Ale..chenski
    Commented Mar 22 at 2:28
  • \$\begingroup\$ @Ale..chenski It has been done in evolutionary algorithm research where totally crazy things were implemented that would not be allowed by conventional design tools. This was not systematic design though. I don't know how closely the researchers were working to the bitstream though; Whether the algorithm was set loose with just ones and zeroes and had to learn the bitstream protocol on its own, or if it worked with higher level objects. \$\endgroup\$
    – DKNguyen
    Commented Mar 22 at 3:25
  • \$\begingroup\$ What are the specific requirements of the 80 MHz signal? Does it need to be symmetrical? How much jitter is allowed? For example, you can design something that "drops" every 5th clock of the 100 MHz input... \$\endgroup\$
    – the busybee
    Commented Mar 22 at 6:31

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