Fermi levels in MOS capacitor

Question

I have a question about the Fermi level, for example in a MOS capacitor under an external voltage Vg:

We know that a MOS capacitor without external voltage (ie in equilibrium) has a uniform and straight Fermi level in space.

When an external voltage is applied, the Fermi level splits into two levels - one in the metal and one in the semiconductor, where the difference between them depends on the applied voltage.

My question is why Fermi levels are uniform on each side separately - on the side of the metal the Fermi level is straight, and also on the side of the semiconductor it is straight (and as we said they are not at the same height)?

Answer 1

An imprecise way of thinking about this is as follows. A gradient in a Fermi level provides a driving force for the motion of carriers, so if there are carriers there will be a current. In the semiconductor there is no current because current is blocked by the insulator, so the gradient of the Fermi level must be zero and the Fermi level must be flat.

A more precise explanation involves electron and hole quasi-Fermi levels.