Detection of simultaneous edges of two asynchronous clocks

Question

This question was initially asked at StackOverflow as a Verilog question, but, eventually, it became more hardware than software discussion.

The question: how simultaneous (positive) edges of two asynchronous clocks might be detected in digital circuit.

The original question did not contain any information about how much time "simultaneous" is, therefore your suggestions and thoughts on this are also welcome. For clarity, let's define "simultaneous" as 0.5 or 0.25 times the period of the slower clock.

One of the proposed solution uses non-standard flip-flop configurations described in the following patents: US6320442 B1, US5793236 A, US5327019 A. Is this approach 100% safe, or there is still chance of overlooking the event in question (due to internal metastability, or any other reason)?

Is there a standard approach in dealing with this kind of tasks?

EDIT:

There were few solutions suggested, but none showed explicitly how exactly the information about the occurrence of simultaneous edges may be (reliably) fed into digital logic. Please note that (essentially) this is the question, and any solution which do not address this subject is incomplete.

Answer 1

I don't think this should be difficult. Assuming you have master clock that is faster than either of Async clocks, all you need is 2 sets of double synchronizers and a state machine running in master clock domain to "detect" events. This setup will give resolution of 2 cycles in master clock domain for definition of "simultaneous". So that will dictate what minimum frequency master clock should be.

^{simulate this circuit – Schematic created using CircuitLab}

It is absolutely important that ClkA and Clkb are true clock signals without transients. If these were termed as simple signals, I would add a flip flop in front of synchronizer in that clock domain as such.

^{simulate this circuit}

State machine should be straight forward where any transitions from 00 to 11 or 00->01/10->11 happening in 1 or 2 cycles.

Answer 2

The simplest pure-hardware way would be the circuit below.

^{simulate this circuit – Schematic created using CircuitLab}

This works because there's a propagation delay through the inverters. During that propagation delay, the bottom two inputs will still be high, pulsing the output of the NAND gate. You just have to make the propagation delay long enough to satisfy the setup and hold times of the NAND, but short enough that it will completely discharge between clock cycles.

It's timing sensitive but definitely doable. People do it by accident all the time.

Answer 3

I've edited my answer to show the circuit diagram with more detail and also cover the questions in the comments from David Kessner and Vasiliy Zukanov: -

Two gates are used; the OR gate has to be zero before a timer clocked with what I've called "super-clock" is primed. Once it is primed it then starts counting as soon as either CLK1, CLK2 or both go high.

It finishes timing as soon as a zero is detected on the output of the EXOR gate.

2nd EDIT to provide information that is a little clearer.

Super-clock is a clock running significantly higher than CLK1 or CLK2. The period of super-clock is many times smaller than the period of either CLK1 or CLK2.

If the timer doesn't count to anything after being primed and triggered it is because the positive edge time difference between CLK1 and CLK2 is insignificant.

If it counts to 1 and no more then it can be assumed that the time delay between CLK1 and CLK2 is between zero and one-super-clock period i.e. it is still insignificant. If it counts to two or higher than this can be arbitrarily taken as the two clocks not rising synchronously.