# Circuit with two clocks

Most digital circuits can be built in more than one way. However, the easiest way I've seen to build an edge-triggered D flip-flop is with a pair of D latches. One has WRITE connected to CLOCK, the other has WRITE connected to the inverse of CLOCK. This way, one latch is always write-enabled, and which one changes whenever the level of CLOCK changes.

simulate this circuit – Schematic created using CircuitLab

What I ended up doing is to have two separate clock inputs instead. This way I can ensure that they're never both high at the same time; I can put some dead time where both of them are low.

simulate this circuit

Is it common to do something like that? Have I reinvented a common technique that has a name? Or is this a totally off-the-wall crazy way to design circuits?

• Why not use one d type to clock in data? Why the added complication? Explain the benefit? – Andy aka Feb 1 '20 at 11:40
• @Andyaka The benefit is that a level-sensitive latch is smaller and uses less power than an edge-triggered flip-flop. – Elliot Alderson Feb 1 '20 at 17:28
• i Think the op should explain what he was trying to achieve. – Andy aka Feb 1 '20 at 19:10