Circuit with two clocks

Question

Most digital circuits can be built in more than one way. However, the easiest way I've seen to build an edge-triggered D flip-flop is with a pair of D latches. One has WRITE connected to CLOCK, the other has WRITE connected to the inverse of CLOCK. This way, one latch is always write-enabled, and which one changes whenever the level of CLOCK changes.

^{simulate this circuit – Schematic created using CircuitLab}

What I ended up doing is to have two separate clock inputs instead. This way I can ensure that they're never both high at the same time; I can put some dead time where both of them are low.

^{simulate this circuit}

Is it common to do something like that? Have I reinvented a common technique that has a name? Or is this a totally off-the-wall crazy way to design circuits?

Answer 1

Multi-phase non-overlapping clocks were (are?) often used in semiconductor logic design. This is due to the possibility of very large worse case skews (max vs. min propagation) in the rise/fall edges of a single clock's distribution, especially in non-symmetric technologies, such as depletion-mode NMOS (no P transistors). So two edges of the same polarity are distributed instead.

Another variation is overlapping quadrature clock systems.

Answer 2

Yes this is, or at least has been common. Many chips of the 80's required two-phase non-overlapping clocks to do their function.

Answer 3

One time you would do something like what you showed in the 2nd schematic that is when passing data or a signal from one clock domain (CLOCK1) to another (CLOCK2), though what you have shown is not sufficient. The output of the 2nd flip flop (Q) could exhibit metastable operation, which would need to be addressed with some additional logic and flip flops downstream.