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Most digital circuits can be built in more than one way. However, the easiest way I've seen to build an edge-triggered D flip-flop is with a pair of D latches. One has WRITE connected to CLOCK, the other has WRITE connected to the inverse of CLOCK. This way, one latch is always write-enabled, and which one changes whenever the level of CLOCK changes.

schematic

simulate this circuit – Schematic created using CircuitLab

What I ended up doing is to have two separate clock inputs instead. This way I can ensure that they're never both high at the same time; I can put some dead time where both of them are low.

schematic

simulate this circuit

Is it common to do something like that? Have I reinvented a common technique that has a name? Or is this a totally off-the-wall crazy way to design circuits?

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  • \$\begingroup\$ Why not use one d type to clock in data? Why the added complication? Explain the benefit? \$\endgroup\$ – Andy aka Feb 1 at 11:40
  • \$\begingroup\$ @Andyaka The benefit is that a level-sensitive latch is smaller and uses less power than an edge-triggered flip-flop. \$\endgroup\$ – Elliot Alderson Feb 1 at 17:28
  • \$\begingroup\$ i Think the op should explain what he was trying to achieve. \$\endgroup\$ – Andy aka Feb 1 at 19:10
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Multi-phase non-overlapping clocks were (are?) often used in semiconductor logic design. This is due to the possibility of very large worse case skews (max vs. min propagation) in the rise/fall edges of a single clock's distribution, especially in non-symmetric technologies, such as depletion-mode NMOS (no P transistors). So two edges of the same polarity are distributed instead.

Another variation is overlapping quadrature clock systems.

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Yes this is, or at least has been common. Many chips of the 80's required two-phase non-overlapping clocks to do their function.

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One time you would do something like what you showed in the 2nd schematic that is when passing data or a signal from one clock domain (CLOCK1) to another (CLOCK2), though what you have shown is not sufficient. The output of the 2nd flip flop (Q) could exhibit metastable operation, which would need to be addressed with some additional logic and flip flops downstream.

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  • \$\begingroup\$ But the question is not about crossing beween different clock domains, but using a two-phase clocks that never overlap. \$\endgroup\$ – Justme Feb 1 at 12:29
  • \$\begingroup\$ @Justme - you may be right. The OP is not clear, at least in my view, when he says "What I ended up doing is to have two separate clock inputs instead." He doesn't say that the two clocks in the second example are related; just that he can ensure that they are not high at the same time. \$\endgroup\$ – SteveSh Feb 1 at 13:38

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