Verilog gate-level modelling of the JK flip-flop

Question

I am trying to use gate level to model a JK flip-flop to show the Q and Qbar toggling effect. The problem is that when programmed into the device, only the Qbar is toggling while Q is constantly on.

How do I make both Q and Qbar toggle in sequence? So I can show the race condition.

My device is a BASYS3 from Digilent, and my code is:

module JK_gate(q,qbar,clk,j,k);


input j,k,clk;
output q,qbar;

wire nand1_out; // output from nand1
wire nand2_out; // output from nand2
wire new_clk;
    clk_div wrapper(
    .clk(clk),
    .divided_clk(new_clk)
    );

nand(nand1_out, j,new_clk,qbar);
nand(nand2_out, k,new_clk,q);
nand(q,qbar,nand1_out);
nand(qbar,q,nand2_out);
endmodule

The clock divider is:

module clk_div(
    input wire clk,
    output reg divided_clk = 0
    );

localparam div = 50000000;
//division value = 100 MHz/(2 x desired frequency)

integer counter_val = 0;
always@ (posedge clk)
begin
    if (counter_val == div) counter_val <= 0; //reset
    else counter_val <= counter_val +1; //count +1
end

always@ (posedge clk)
begin
    if (counter_val == div) divided_clk <= ~divided_clk; //flip the signal
    else divided_clk <= divided_clk; //signal stays
end  
endmodule

The simulation that I am trying to get to work is, for this I removed the clock divider in the original code to remove 1 layer of complexation.

module jk_sim;
reg j, k, clk;
wire q, qbar;

JK_gate U0(q,qbar,clk,j,k);

initial begin
j=1'b0;
k=1'b0;
clk=1;

#100
j=1'b1;
k=1'b0;

#100
j=1'b0;
k=1'b1;

#100
j=1'b1;
k=1'b1;
end

always #25 clk=~clk;
endmodule

Answer 1

What you have created is a JK latch and not a JK flip-flop. The reason you are getting high impedance Z or don't care X in your output is because the simulator does not know what the initial state of Q or Qbar is. When we do hand analysis, we assume some initial state but that is not the case with a simulator.

You need to use the "force " keyword to force the initial state to either 0 or 1.

Also, I'm not sure if still the simulator will show the race around condition. If you want a proper functioning flip-flop it is better to use master-slave flip-flop.

You also need to "release" the q, qbar values after some time so that they can change depending on your circuit.

Try this testbench:

module jk_sim;
reg j, k, clk;
wire q, qbar;

JK_gate U0(q,qbar,clk,j,k);

initial begin

j=1'b0;
k=1'b0;
clk=1;
force q = 1'b0;
force qbar = 1'b1;
#10 release q;
release qbar;

#10
j=1'b1;
k=1'b0;

#20
j=1'b0;
k=1'b1;

#10
j=1'b1;
k=1'b1;
#500 $finish;
end

always #2 clk=~clk;
endmodule
```