Operation of this CMOS Logic

Question

I found this CMOS circuit in my textbook. It says that when input voltage is 0V, the output voltage is 0V, and IDN and IDP are both zero. I think that the output voltage is 0V due to some form of symmetry. However, I could not understand as to why IDN and IDP are both zero. Could anyone please explain? Thanks.

Answer 1

Both transistors would have Vgs below their respective threshold voltage, so only leakage current would flow Drain-to-source.

Consider this circuit as two complementary source-followers connected together, each with 20K source resistors.