Why does Flash and SRAM have a "hold" signal?

Question

I have read datasheets on SRAM and Flash devices. They seem to have a "Hold" signal that can be used to prevent it from registering the input data/instructions until it the hold signal is deasserted. When would one need to use such a thing?

The 23LC1024 SRAM datasheet says: "The HOLD pin is used to suspend transmission to the 23A1024/23LC1024 while in the middle of a serial sequence without having to re-transmit the entire sequence over again"

These memory devices also have dual and quad SPI modes in which the hold signal is replaced with a data IO signal instead. This makes me think that the hold signal is not really important or is it?

Answer 1

I think the purpose is so that exception software can do other things with the SPI bus while your code is in the middle of a transaction. I suppose it is possible to do that if you design everything very carefully, but it raises more issues that it solves. If interrupt code really needs to have low latency access to a particular device, you should probably put that device on its own bus.

However, in general, interrupt code shouldn't be trying to do something as slow as SPI transactions anyway. A much better strategy is to employ a proper software architecture so that multiple tasks can use the SPI bus serially by use of a mutex. I have done this several times, and it makes multiple asynchronous SPI tranactions pretty easy and reliable without stepping on each other.

Basically, bus sharing shouldn't be done at such a low level that individual chips need to be suspended in the middle of a transaction while something else uses the bus. That's a hardware bandaid to deal with poorly thought out software.

Answer 2

As well as what the other answers have stated, the pin also has a use in DMA transfers. In one design I had an SPI based MP3 codec IC which required data to be copied from Flash memory (could also be SRAM) to the IC using the same data bus (due to having only one hardware SPI bus on the MCU I was using).

The process here is essentially: (1) set the start address in the memory, (2) read a small chunk of data, (3) put the memory is suspend mode, (4) write the chunk of data back out to the MP3 codec, and (5) bring the memory out of suspend mode and jump back to 2.

The advantage of this process is it is a lot faster to toggle the suspend pin between each chunk of data than it is to start a new read from the memory. To start a read you usually have to send at least 3 bytes (command + address) to the memory which takes many, many more clock cycles than just toggling the hold pin between data chunks while you use the bus for something else.

Answer 3

The only way I've used the hold signal is to attach an RC network to prevent the FLASH from reading incorrect data during power up. I think one of the FPGAs I was using at the time had an unspecified behavior on its configuration pins before the power lines have settled. Effectively this is a second chip select.

Another useful application is when you need to read information from a secondary memory chip on the same bus mid-transmission in time critical applications. You do not need to wait for the SPI to finish its message and can resume it later.