ERROR:Xst:827, Signal next_states1 cannot be synthesized, bad synchronous description

Question

it shows

ERROR:Xst:827 - "C:/Users/namec/Desktop/Class/VHDL/Traffic_Light/Traffic_lig‌​ht.vhd" line 46: Signal next_states1 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Highway: process(CLk) 
    variable counter: integer := 0;    
begin
    case traffic_states1 is
        when H0 => 
            if (Input='0' and rising_edge(clk)) then 
                next_states1 <= H0;
                counter := counter + 1;
            elsif (counter <=20) and rising_edge(clk) then
                next_states1 <= H0;
                counter := counter + 1;
            elsif Input='1' and rising_edge(clk) and (counter >20) then
                next_states1 <= H1;
                counter := 0;
                -- else next_states1 <= traffic_states1;
            end if;
        when H1 =>     
            if counter = 3 and rising_edge(clk) then
                next_states1 <= H2;
                counter := 0;
            else
                next_states1 <= H1;
                counter := counter + 1;    
            end if;
        when H2 =>
            if rising_edge(clk) and counter = 9 then
                next_states1 <= H0;
                counter := 0;
            else
                next_states1 <= H2;
                counter := counter + 1;
            end if;
        when others =>
            null;

Answer 1

I think it would be good for you to do a course in or tutorial on VHDL... But anyhow: the clock edge detection should not be inside the case statement this way.

Highway: process(CLk) 
    variable counter: integer := 0;    
begin
    if rising_edge(clk) then
        case traffic_states1 is
            when H0 => 
                if (Input='0') then 
                    next_states1 <= H0;
                    counter := counter + 1;
                elsif (counter <=20) then
                    next_states1 <= H0;
                    counter := counter + 1;
                elsif (Input='1' and counter >20) then
                    next_states1 <= H1;
                    counter := 0;
                    -- else next_states1 <= traffic_states1;
                end if;
            when H1 =>     
                if (counter = 3) then
                    next_states1 <= H2;
                    counter := 0;
                else
                    next_states1 <= H1;
                    counter := counter + 1;    
                end if;
            when H2 =>
                if (counter = 9) then
                    next_states1 <= H0;
                    counter := 0;
                else
                    next_states1 <= H2;
                    counter := counter + 1;
                end if;
            when others =>
                null;