0
\$\begingroup\$

it shows

ERROR:Xst:827 - "C:/Users/namec/Desktop/Class/VHDL/Traffic_Light/Traffic_lig‌​ht.vhd" line 46: Signal next_states1 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Highway: process(CLk) 
    variable counter: integer := 0;    
begin
    case traffic_states1 is
        when H0 => 
            if (Input='0' and rising_edge(clk)) then 
                next_states1 <= H0;
                counter := counter + 1;
            elsif (counter <=20) and rising_edge(clk) then
                next_states1 <= H0;
                counter := counter + 1;
            elsif Input='1' and rising_edge(clk) and (counter >20) then
                next_states1 <= H1;
                counter := 0;
                -- else next_states1 <= traffic_states1;
            end if;
        when H1 =>     
            if counter = 3 and rising_edge(clk) then
                next_states1 <= H2;
                counter := 0;
            else
                next_states1 <= H1;
                counter := counter + 1;    
            end if;
        when H2 =>
            if rising_edge(clk) and counter = 9 then
                next_states1 <= H0;
                counter := 0;
            else
                next_states1 <= H2;
                counter := counter + 1;
            end if;
        when others =>
            null;
\$\endgroup\$
  • \$\begingroup\$ it shows ERROR:Xst:827 - "C:/Users/namec/Desktop/Class/VHDL/Traffic_Light/Traffic_light.vhd" line 46: Signal next_states1 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release. \$\endgroup\$ – Yuan Cao Mar 21 '17 at 4:42
  • 1
    \$\begingroup\$ Please post a problem description and a question, its a little unclear, edit your question and try again. \$\endgroup\$ – Voltage Spike Mar 21 '17 at 5:17
  • \$\begingroup\$ You have to take the original question and your comment and make a proper question out of them. The title is not where the question goes. Thanks. \$\endgroup\$ – TonyM Mar 21 '17 at 9:53
  • 1
    \$\begingroup\$ move the "if rising_edge(clk)" outside the case statement. \$\endgroup\$ – ks0ze Mar 21 '17 at 11:40
0
\$\begingroup\$

I think it would be good for you to do a course in or tutorial on VHDL... But anyhow: the clock edge detection should not be inside the case statement this way.

Highway: process(CLk) 
    variable counter: integer := 0;    
begin
    if rising_edge(clk) then
        case traffic_states1 is
            when H0 => 
                if (Input='0') then 
                    next_states1 <= H0;
                    counter := counter + 1;
                elsif (counter <=20) then
                    next_states1 <= H0;
                    counter := counter + 1;
                elsif (Input='1' and counter >20) then
                    next_states1 <= H1;
                    counter := 0;
                    -- else next_states1 <= traffic_states1;
                end if;
            when H1 =>     
                if (counter = 3) then
                    next_states1 <= H2;
                    counter := 0;
                else
                    next_states1 <= H1;
                    counter := counter + 1;    
                end if;
            when H2 =>
                if (counter = 9) then
                    next_states1 <= H0;
                    counter := 0;
                else
                    next_states1 <= H2;
                    counter := counter + 1;
                end if;
            when others =>
                null;
\$\endgroup\$
  • \$\begingroup\$ Thanks! Do you know why clock edge detection can not in case statement? \$\endgroup\$ – Yuan Cao Mar 21 '17 at 16:32
  • \$\begingroup\$ Well, it can, but not how you are using it. You can't use it 'sometimes' like in your code. As the error shows, it is very difficult to generate logic from this; the synthesis software couldn't do it. But you are making a state machine, so it should probably all be synchronous. \$\endgroup\$ – JHBonarius Mar 21 '17 at 18:30

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