VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description

Question

I am wondering why synthesizing this code doesn't work, but simulating does. ONLY WHEN TRYING TO SYNTHESIZE I get the following error:

Signal sig_enable cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Here is my code:

architecture Behavioral of myModule is
signal sig_outSerial: std_logic := '1';
signal tri_output: std_logic := '1';
signal sig_enable: std_logic := '0';
signal sig_done: std_logic := '1';

component triBuffer
    port(
    input: in std_logic;
    control: in std_logic;
    output: out std_logic
    );
end component;

begin

U1: triBuffer port map(input => CLK_IN, control => sig_enable, output => tri_output);

process(tri_output, SEND)
    variable i: integer := 0;
begin
    if falling_edge(tri_output) and sig_enable = '1' then
        if i = 8 then
            i := 0;
            sig_enable <= '0';
            sig_outSerial <= '1';
            sig_done <= '1';
        else
            sig_outSerial <= inByte(i);
            i := i + 1;
            sig_done <= '0';
        end if;
    end if;

    if rising_edge(SEND) then
        sig_enable <= '1';
    end if;
end process;

outSerial <= sig_outSerial;
done <= sig_done;
CLK_OUT <= tri_output;

end Behavioral;

Answer 1

Your code has two ways to change sig_enable

if falling_edge(tri_output) and sig_enable = '1' then
    if i = 8 then
        i := 0;
        sig_enable <= '0';

...

if rising_edge(SEND) then
    sig_enable <= '1';
end if;

So you are asking for sig_enable to change on either a falling edge of tri_output or a rising edge of SEND.

There is no off-the-shelf latch or flip-flop that can do this, and that's why the design can't be synthesized.

In an ASIC design, you might be able to achieve what you want with a SR latch. But you'd need to write code that reflects the actual behavior of an SR latch (level sensitive rather than edge sensitive).

In an FPGA design it would be more usual to use SEND as a combinatorial input to the logic that changes sig_enable when clocked by tri_output or by a fast-running clock (depending on your timing requirements).