How to implement derivative, and create a delay of dozens of clock cycles?

Question

I have uart entity which have the following signals (I write only the relevant - for tx)

-- The output data: 8 bit - this is the UART receiver
-- Data is only valid during the time the STB is high
-- Acknowledge the data with a pulse on ACK, which is confirmed by
-- revoking STB.
-- When the following start bit is received the data becomes
-- invalid and the STB is revoked. So take care about fetching the
-- data early enough, or install your own FIFO buffer
DATA_STREAM_OUT     : out std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : out std_logic;
DATA_STREAM_OUT_ACK : in  std_logic;
TX                  : out std_logic;

I have another block which its enable input should changed to high for only one clock when there is a change of the DATA_STREAM_OUT_ACK (high to low) plus delay of 50 clk cycles.

I guess I should derive DATA_STREAM_OUT_ACK, but I'm not sure hot to implement this, and also the delay (may be with counter).

Answer 1

This will do the function you asked about. You may have to adjust the '51' constant to get your precise timing.

  signal delayCtr       : natural range 0 to 51;

  Delayed : process(RST, CLK) is
  begin
    if (RST = '1') then
      delayCtr     <=   0 ;
      delayedEn    <=  '0';

    elsif rising_edge(clk) then

      if (data_stream_out_stb = '1') then
        delayCtr   <=  51;

      elsif (delayCtr > 0) then
        delayCtr   <=  delayCtr - 1;

      end if;

      if (delayCtr = 1) then
        delayedEn  <=  '1';
      else
        delayedEn  <=  '0';
      end if;

    end if;
  end process Delayed;

You'll obviously have to wire it into the rest of your VHDL yourself, providing clock and reset. Otherwise we'll have an eternal comment exchange. But it shows the operating principle of the solution.