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I'm so confused between cas latency and access time between cpu and memory.

According to this wikipedia page, reading 8 word from ddr3-1600 sdram takes 15~ns,so between memory controller and sdram there is only 15~ns latency for reading 8 word.

But according to this and other sources mention that access time between cpu and (local)memory is 60-100ns?!

So where that extra 40-80ns comes from?

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  • \$\begingroup\$ It's because there's more to reading memory than just using /CAS, as you must have wondered. Have a look on the interweb, there's plenty of text on it. Also, take a look at an SDRAM datasheet, the Micron ones are good. It's not a question for this site, this is just tutorial stuff. Good luck with it all. \$\endgroup\$
    – TonyM
    Commented Apr 9, 2017 at 13:51
  • \$\begingroup\$ I will note that the Stackoverflow reference is at the system level not the raw interface. \$\endgroup\$
    – Peter Smith
    Commented Apr 9, 2017 at 13:59
  • \$\begingroup\$ As Tony says - the diagrams in a DRAM data sheet should make it clear enough. \$\endgroup\$
    – Russell McMahon ♦
    Commented Apr 9, 2017 at 14:04

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Between the CPU and memory in a CPU is 3 layers of cache: L1, L2 and L3. You've got to get all 3 of those caches to "miss" before you'll ever touch memory. Even after you touch memory, that data has to then feed back down the cache hierarchy before populating L1 and the registers to actually use the data.

It might seem wasteful, but the advantage of this is that if you try and keep your data in L1, you can operate on it much faster than any sort of memory. This is where a lot of software performance improvements can come from if you understand the hardware underneath.

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