Declare queue in verilog

Question

I wrote a simple code to declare a queue and use it in verilog, but it always gives an error when I use ISE 14.6 synthesize tool.

module queues; 
byte qu [$] ;

initial
begin
qu.push_front(2);
qu.push_front(12);
qu.push_front(22);
qu.push_back(11);
qu.push_back(99);
$display(" %d ",qu.size() );
$display(" %d ",qu.pop_front() );
$display(" %d ",qu.pop_back() );
qu.delete(3);
$display(" %d ",qu.size() );
end
endmodule

These are the errors:

1. Syntax error near "$"
2. byte is an unknown type
3. Module ignored due to previous errors.

So what will be the problem? Is there any library that should be included ??!!

Answer 1

Queues are SystemVerilog and they are not synthesizable. Queues are intended only to be used in simulation for verification and behavioral modeling.

If you want a queue functionality to synthesize, then you must create an fixed sized array and manage the pointer(s).

SystemVerilog and Verilog have features only usable in simulation. They language itself does provide requirements on what should and shouldn't be synthesizable. It is up the the creator of the synthesizer to decide that it can support. Most synthesizers have very similar support (no one wants to be outdone by a competitor). But some stuff is inherently hard or impractical to synthesize. In general to be synthesizable, the definition and attributes need to be static. A queue has a dynamic size therefore not synthesizable.