What are common ways that modern processors handle data hazards with asynchronous registers

Question

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it.

Specifically, I'm implementing control and status registers (CSRs), which allows the system to be controlled to a greater degree.

These CSRs do not need an instruction to be altered, they can change based on the state of the machine. This comes with a set of data hazards that I have been trying to solve. There are not many existing resources that offer solutions to these hazards.

Rules:
All instructions which associate with these registers are atomic instructions which are meant to swap the CSR value with a general purpose value.

Hazard 1: RAW
The register is read from, and the CSR are read from on one clock cycle of the pipeline. On the next clock cycle, the values are written. During this time, the CSR may have changed.

Hazard 2: interrupt WAW Something in the processor triggers an interrupt, And changes a whole bunch of registers at once. In the pipeline, however, there is an instruction which writes to a CSR which has been modified. This corrupts the register.

What are some common ways to remedy these hazards?

Answer 1

In general any asynchronous inputs to the system (such as from peripherals) would be synchronized with a dual rank register to make it synchronous to the processor clock before it is used by any processor state machine.

From: Synchronization in digital logic cercuits

Answer 2

I'm not sure about your question. Register updates are usually committed in the write state, that includes normal registers, the program counter and system registers.

If an exception is triggered (for example after a memory access), the updates can be cancelled. For example the program counter that is always in advance for fetches, this register has several copies along the pipeline with different "ages".

For things that affect performances, like NZVC flags in CPUs that use them, these flags will be bypassed like integer registers around the ALU. For less performance sensitive system flags and registers, the pipeline can stall after one of the instructions controlling these flags is decoded, until the pipeline is empty, for example instructions that controls interrupt masking flags.