Questions tagged [risc-v]
For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use.
38 questions
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RISC-V Exercise: why is `MemtoReg = 1`?
Given the instruction sd x12, 20(x13) (ISA RV64I), what are the inputs and outputs of the encircled MUX?
My answer: if x[n] is ...
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Wrong solution to a short RISC-V exercise
We are told that a RISC-V exercise with no data forwarding executes the instruction add x3,x2,x1, followed by sw x3, 16(x8). My ...
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Displaying motor RPM effectively
I have a softcore RISC-V CPU running on an FPGA that is controlling a DC motor very simply with a PI controller. There are 7-segment displays for the user to vary the speed setpoint and another 7-...
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CH32V003 max GPIO current
I am trying to find what current can a GPIO of CH32V003 (the 10cent MCU) output. Its noticeably chinese english datasheet states (on p.21)
GPIO (General-Purpose Input/Output Port) can sink or output ...
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What does this mean in RISC-V opcode table
I want to check my understanding of how the imm[20|10:1|11|19:12] specifies the bit arrangements in the JAL (jump and link) instruction in RISC-V architecture?
I ...
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What is the injector pipeline stage in this RISC-V core?
The cores in the Efinix Sapphire SOC FPGA IP core have 6 pipeline stages (fetch, injector, decode, execute, memory and write back).
What is or might be the injector stage? I can't find it explained ...
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What Specific Optimizations Can ARM Implementations Do That x86 Ones Cannot (And Vice-Versa And Risc-V)
I believe this question is slightly different from others (ex: Why exactly does the x86 (primarily x86-64) instruction set consume more power than reduced instruction sets like arm?)
This question is ...
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Memcopy Instruction in Risc V
I designed a Risc V 32-bit single cycle processor without pipelining for a project. We are given to implement a new instruction called "Memcopy". It copies an array of size N from one ...
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RISC-V byte load and store
I have the confusion in the following RISC V programming statements. Can someone explain that why does the contents of s0 in the last comment shown. shouldn't it be 0x00000180 the same as we are not ...
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What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
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What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
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Why do we shift by three in RISC-V loops?
In this youtube video, the instructor explained some basic code in RISC-V assembly, but i didn't understand why in the first line, he is shifting i by 3. Why do we have to multiply it by 8??
I feel ...
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Signal not Showing State Changes on Intergrated Logic Analyser (Vivado)
I have been using the Integrated Logic Analyser (ILA) on Vivado 2021.2 to log some signals from a RISC-V processor running on an FPGA (BASYS 3 FPGA development board).
The signals I am monitoring are ...
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Why using RISC-V over off-the-shelf chips is more energy efficient?
I am not an expert on the world of chips, but as a developer, I understand quite well how they work and what problem each chip solves.
I have been increasingly curious about RISC-V and, among other ...
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RISC-V Zero Instruction Question
I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.
Does anybody know what happens ...
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How different layers of cache connect in hardware?
I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:
Does the unified L2 Cache have dual port ...
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Generating Control Signals via Case statement vs Boolean function
I'm building a RISC-V processor recently, and I've encountered a question when constructing the control unit. That is, what's the difference between generating control signals through:
Case statement,...
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How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
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What is preferred way to have an interrupt every second - setting timecmp to timecmp+1000 or time+1000
me and friend were discussing what the most accurate way have an timer interrupt happen every second in RISC-V. We understand that the internal clock is generally inaccurate, but were still wondering ...
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How we are giving values to source registers in instruction set architecture?
This figure represents RISC-V R-type instruction. Let assume this instruction is for add operation. When this instruction is given to the processor it adds rs to rt.
My question is how rs and rt ...
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classic RISC pipeline: Why does memory access stage comes before register file write back?
Here are two confusions:
Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers?
It seems that once the execution ...
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Is AXI a good interface for outside communications?
Suppose if we want to get some data from some ADCs, which are placed in a separate chip, and process that data in RISC-V processor. I was looking for an interface to define/use inside the RISC-V chip ...
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RISC-V: How do you store specific values in large addresses in Venus (RISC-V sim)?
I'm new to RISC-V and I'm having trouble understanding how one would store specific values in large addresses. For example, if I wanted to store the value 5 in 0x12312312, how would you go about that?
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How to choose the memory size to port a soft from 68HC11 8bit to RISC-V based MCU 32bits target [closed]
I have to build a new hardware with a new 32bit microcontroller. I have a working project on an 8bit microconttroller.
When compiling the C program for my new target what will be the needed size of ...
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What is a hardware thread in RISC-V?
RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread).
Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged ...
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Store byte instruction in RISC-V assembly
I have a short snippet of RISC-V assembly that I'm having trouble understanding. I'm not sure if I'm interpreting the instructions wrong, from my interpretation it seems as if the branch (BNE) will be ...
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Where is the RAM stored on a RISC-V CPU? [closed]
Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
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Offset of bnez in RISC-V program
I came across a question about assembly that I was confused on.
We are given the following table for addresses and instructions:
The question says: replace the labels of PC-relative targets with ...
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Help in understanding Store Word (SW) instruction in Risc-V
So this is what I understood from what my professor said, but I don't think it's the right answer. What am I doing wrong? I'm sure It's just some small thing that I'm getting mixed up.
Given ...
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Forwarding in RiscV multi cycle Pipeline
Any idea could be helpful
I have been trying for days to understand forwarding mechanism in RiscV but unfountly I keep failing, so I though about asking basic question to make sure I am building on ...
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RISC-V assembly lui?
In RISC-V assembly I wrote:
addi s0,x0,0x20000
Is this legal such that the assembler will prove the command and make it work right or I'm forced to change it to:
<...
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Why we can't do forward in RiscV?
While studying forwarding in RiscV cpu I saw the following claim:
But I can't understand why we can't do forward in this case, why in different conditions we were able to do this and now we can't?
It ...
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RiscV assembly, function arguments
I learnt that in RiscV assembly we save function arguments in registers s0,...,s7 but what if I had more that 8 arguments?
Plus what about the case where I have more than 32 arguments (let's say 40) ...
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RiscV CPU, why is it so complicated? (for companies to build)
I saw an online code for RiscV32 bit processor which consists of nearly 1000 lines of code and supports all know commands like sw, lw, j, etc...
My question is, why companies like Apple need so much ...
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Assembly code, what does it do?
I'm interested to know what this assembly code do knowing that X1 is full of zeroes.
...
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Best way to optimize verilog cpu?
I wrote a riscv core in verilog which works fine, but is slow. It can't go faster than 50mhz when synthesizing in Xilinx ise for spartan 6. I have however seen similar cores be able to go to 100mhz or ...
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What are common ways that modern processors handle data hazards with asynchronous registers
I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it.
Specifically, I'm implementing control and status registers (CSRs), which ...
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Is this the correct truth table to determine whether or not to execute an interrupt in a RISC V system?
I'm working on implementing the privileged RISC V ISA, which can be found here.
I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly:
Global interrupt-...
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