Questions tagged [risc-v]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use.

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How we are giving values to source registers in instruction set architecture?

This figure represents RISC-V R-type instruction. Let assume this instruction is for add operation. When this instruction is given to the processor it adds rs to rt. My question is how rs and rt ...
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classic RISC pipeline: Why does memory access stage comes before register file write back?

Here are two confusions: Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers? It seems that once the execution ...
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Is AXI a good interface for outside communications?

Suppose if we want to get some data from some ADCs, which are placed in a separate chip, and process that data in RISC-V processor. I was looking for an interface to define/use inside the RISC-V chip ...
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RISC-V: How do you store specific values in large addresses in Venus (RISC-V sim)?

I'm new to RISC-V and I'm having trouble understanding how one would store specific values in large addresses. For example, if I wanted to store the value 5 in 0x12312312, how would you go about that?
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How to choose the memory size to port a soft from 68HC11 8bit to RISC-V based MCU 32bits target [closed]

I have to build a new hardware with a new 32bit microcontroller. I have a working project on an 8bit microconttroller. When compiling the C program for my new target what will be the needed size of ...
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What is a hardware thread in RISC-V?

RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread). Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged ...
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Store byte instruction in RISC-V assembly

I have a short snippet of RISC-V assembly that I'm having trouble understanding. I'm not sure if I'm interpreting the instructions wrong, from my interpretation it seems as if the branch (BNE) will be ...
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Where is the RAM stored on a RISC-V CPU? [closed]

Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
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Offset of bnez in RISC-V program

I came across a question about assembly that I was confused on. We are given the following table for addresses and instructions: The question says: replace the labels of PC-relative targets with ...
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Help in understanding Store Word (SW) instruction in Risc-V

So this is what I understood from what my professor said, but I don't think it's the right answer. What am I doing wrong? I'm sure It's just some small thing that I'm getting mixed up. Given ...
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Forwarding in RiscV multi cycle Pipeline

Any idea could be helpful I have been trying for days to understand forwarding mechanism in RiscV but unfountly I keep failing, so I though about asking basic question to make sure I am building on ...
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RISC-V assembly lui?

In RISC-V assembly I wrote: addi s0,x0,0x20000 Is this legal such that the assembler will prove the command and make it work right or I'm forced to change it to: <...
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Why we can't do forward in RiscV?

While studying forwarding in RiscV cpu I saw the following claim: But I can't understand why we can't do forward in this case, why in different conditions we were able to do this and now we can't? It ...
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RiscV assembly, function arguments

I learnt that in RiscV assembly we save function arguments in registers s0,...,s7 but what if I had more that 8 arguments? Plus what about the case where I have more than 32 arguments (let's say 40) ...
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RiscV CPU, why is it so complicated? (for companies to build)

I saw an online code for RiscV32 bit processor which consists of nearly 1000 lines of code and supports all know commands like sw, lw, j, etc... My question is, why companies like Apple need so much ...
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Assembly code, what does it do?

I'm interested to know what this assembly code do knowing that X1 is full of zeroes. ...
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Simulating RV32I ALU + load/store instructions using verilog

I'm writing a Verilog code to simulate RISC-V RV32I ALU and Load/Store instructions in Verilog. It contains of 5 parts: regfile.v- which contains the 32*32 registers required for RV32I, decoder.v- ...
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Best way to optimize verilog cpu?

I wrote a riscv core in verilog which works fine, but is slow. It can't go faster than 50mhz when synthesizing in Xilinx ise for spartan 6. I have however seen similar cores be able to go to 100mhz or ...
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What are common ways that modern processors handle data hazards with asynchronous registers

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it. Specifically, I'm implementing control and status registers (CSRs), which ...
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Is this the correct truth table to determine whether or not to execute an interrupt in a RISC V system?

I'm working on implementing the privileged RISC V ISA, which can be found here. I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly: Global interrupt-...
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