Assigning to a parameterized 2d Verilog array

Question

I have a Verilog array defined as :

logic [ 0 : num_elements - 1 ] [ element_width - 1 ] some_array ;

I want to assign every array element with a vector that is all ones: "11...1". I tried this but I get an error:

some_array <= { num_elements { element_width { 1'b1 } } } ;

What's the correct syntax ?

Answer 1

To assign unpacked 2d array in SystemVerilog with a single line:

some_array <= '{ default: '1 };

Verilog cannot be done in a single line. It must use a for-loop:

for ( i = 0; i < num_elements; i = i +1)
  some_array[i] <= {element_width{1'b1}};

Answer 2

Since some_array is all packed, you can do

some_array <= '1;