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Here are two confusions:

  1. Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers?
  2. It seems that once the execution is done by the ALU, the register write back stage should be the next and then that reg file data is mapped back to the memory outside the processor.

Please do enhance the knowledge and correct any mistakes.

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    \$\begingroup\$ How is the result of a fetch supposed to be stored into a register if memory access happens after write back? \$\endgroup\$
    – FUZxxl
    Commented Apr 26, 2022 at 8:14
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    \$\begingroup\$ Answer (1) : by previous instructions. \$\endgroup\$
    – user16324
    Commented Apr 26, 2022 at 10:37
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    \$\begingroup\$ @user_1818839 I suspect the OP wants to know how the previous instruction then does it. In the case of RISC-V, it's done with LUI and ADDI, if the constant to be loaded is to fill the entire register. And there's others for the case of loading PC relative with AUIPC. \$\endgroup\$
    – jonk
    Commented Apr 26, 2022 at 10:57
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    \$\begingroup\$ Lousycoder, you need to show us what you imagine as an alternative that would work or else draw out your case with a specific RISC-V implementation. I've seen a nine stage pipeline, for example. So I need to see what you are looking at, specifically, to walk you through the details and perhaps help with a more serious answer. Regardless, it all does make sense. The problem is in knowing what's in your head. \$\endgroup\$
    – jonk
    Commented Apr 26, 2022 at 11:00
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    \$\begingroup\$ Lousycoder, you may also wish to look at WebRISC-V: Pipelined Datapath Simulation Online and over on the left side load up a pre-canned program to run. If you clock through the process you can see how registers get their values and you will likely see an answer to #2, as well. \$\endgroup\$
    – jonk
    Commented Apr 26, 2022 at 16:34

1 Answer 1

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Let's look at an LW instruction: 0000 0000 0100 0001 0010 0000 1000 0011 (Immediate=4, RS1=2 (SP), RD=1 (RA)):

  1. IR: PC is provided to Instruction Memory as a memory address and the instruction is presented at the ReadInstr output.
  2. IF/ID: ReadInstr output is latched into the IF/ID latch. At this point the immediate value is extended/expanded by the "immediate generator" and the address (RS1=2) is provided to one of the ports of the dual-read-port register memory. (A dummy value for RS2 of 4 is also provided to the second port, but this read result doesn't matter.) Various slices of the instruction bits are also presented to the input of the ID/EX latch. This is where a lot of decode takes place with parallel units picking off various parts of the latched instruction.
  3. ID/EX: The value read from the SP register (2) is latched and presented to the ALU, along with the immediate value of #4 and the "add operation." The ALU presents the sum of the SP register and #4 to its output. The destination register address is also latched here.
  4. EX/MEM: The ALU output (SP+4) is latched as the address presented to the Data Memory and the READ control line is activated to perform a read from Data Memory at the presented address. The value read from this address is now presented and ready to be latched at the next step. The destination register address is copied from the ID/EX and latched into EX/MEM, as well.
  5. MEM/WB: The destination register address is latched here from the EX/MEM stage and the value read from the Data Memory is latched, as well, and presented back to the register file as a Write Register data value, along with the latched register address that has been copied along through the stages. At the next clock, the presented data value will be written into the addressed register.

If the MEM/WB stage were earlier than the EX/MEM stage, then there would be a serious problem for the LW instruction. The write-back stage would occur too early and the data memory accessed too late.

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  • \$\begingroup\$ Okay, so can I say that reg file read must occur "before" data memory write (in case of Store instruction) and data memory read must occur "before" reg file write (in case of Load instruction), right? \$\endgroup\$
    – lousycoder
    Commented Jun 13, 2022 at 8:44
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    \$\begingroup\$ @lousycoder Don't worry about what you've "heard." RISC is not "a single thing." If you want to see a case where the folks went absolutely maximum towards RISC then look at the DEC Alpha processor. That baby is absolutely CRAZY-minded towards RISC. The absolute opposite is the MSP430 from TI. They also say the MSP430 is RISC. That's total crap. It isn't even close. So do NOT listen to folks telling you what RISC is and what RISC is not. Only Patterson and Hennessey have the ultimate say on the topic (my opinion.) (I've met both of them.) \$\endgroup\$
    – jonk
    Commented Jun 13, 2022 at 8:56
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    \$\begingroup\$ @lousycoder As far as what the SW instruction goes, all it does is use the ALU to compute an address while also passing along a register value. This gets to the Data Memory at the EX/MEM stage, where both the address and the register value are presented to the memory system at thee same time. There's no need for WB here. \$\endgroup\$
    – jonk
    Commented Jun 13, 2022 at 8:59
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    \$\begingroup\$ @lousycoder The SW instruction provides a pointer register, an immediate offset to add to the pointer register (using the ALU) to create a data memory address, and a register containing the data to write to memory, and then performs that operation. So it doesn't just set things up. It performs the data write before the instruction retires. And yes, there are lots of register operations. But data memory reads and writes are handled with specialized instructions. That said, functional units (and instructions) can be added. So today's boundaries are not tomorrow's. \$\endgroup\$
    – jonk
    Commented Jun 13, 2022 at 17:42
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    \$\begingroup\$ @lousycoder I am "working" right now and cannot join an active discussion. In a few hours, yes. Just not now. \$\endgroup\$
    – jonk
    Commented Jun 13, 2022 at 17:54

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