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Is there usually a voltage drop across the collector and emitter of a transistor? If so, where is it indicated in the datasheet?

enter image description here

From what I read, the saturation voltage is only a voltage above which the \$\beta\$ relationship starts behaving properly. I don't know if it relates to a voltage drop.

I am looking at NPN transistors for switching purposes. If there is indeed no voltage drop, I plan to connect my load directly to the emitter where the load can theoretically be supplied with \$V=V_C\$ and \$I=\beta I_B\$. Please correct me if my understanding is wrong.

Edit

In response to answers, here is a graph that represents my understanding of saturation from an electronics book:

saturation graph

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The E-C voltage drop in saturation is dependent on the current for a given ratio of base current to collector current. Here is the typical behavior of a 2N4401:

enter image description here

With 100mA of collector current you'll typically see a ~0.14V drop if you drive the base with 10mA. The guaranteed specification, however, is that you'll see less than 0.4V drop at 150mA collector current if you drive the base with 15mA. So you should not count on less than 0.4V.

Note that if you connect the load in the emitter circuit you'll have to drive the base higher than the collector supply by as much as 0.95V in order to get the transistor to saturate. With a current-limiting resistor, that means you might need a couple volts more than the collector supply. Often that is rather inconvenient, but sometimes it is possible.

schematic

simulate this circuit – Schematic created using CircuitLab

Note that if you drive the base from the collector supply you'll typically get almost a volt drop (right hand circuit).

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    \$\begingroup\$ Nicely written out. +1. I think the datasheet the OP shows is from a PNP device. Similar to this OnSemi BC557. Of course, one cannot count on negative values on PNP datasheets, as this OnSemi 2N3906 datasheet illustrates. Even if from the same company. :) \$\endgroup\$
    – jonk
    Commented Jul 4, 2022 at 20:01
  • \$\begingroup\$ Thank you! This explanation is really clear \$\endgroup\$
    – coulombs
    Commented Jul 4, 2022 at 20:33
  • \$\begingroup\$ @jonk It is true. After rechecking, the datasheet is indeed for a PNP device. What's more, it's from OnSemi :) I'm almost certain the website showed me an NPN. \$\endgroup\$
    – coulombs
    Commented Jul 4, 2022 at 20:42
  • \$\begingroup\$ The idea is similar for PNP when you have a load in the emitter, except now you need to drive the base with a voltage below ground to get it to saturate. \$\endgroup\$
    – Spehro 'speff' Pefhany
    Commented Jul 4, 2022 at 20:45
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Notice the "Collector-Emitter Saturation Voltage" specification, three lines from the bottom? That is the minimum voltage from collector to emitter when the transistor is saturated. You won't be able to get zero volts from the collector to emitter...the saturation voltage is the minimum.

When the transistor is not saturated the collector-emitter voltage is determined by the rest of the circuit, so the data sheet can't possibly have this information. However, the data sheet does tell you that this voltage cannot exceed 50 V or the transistor will be damaged.

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  • \$\begingroup\$ What does it mean that Vce "is determined by the rest of the circuit"? Also, from a book I've been reading it says that a transistor is in staturation if Vce is below the saturation voltage. Should it not be the maximum voltage? \$\endgroup\$
    – coulombs
    Commented Jul 4, 2022 at 19:47
  • \$\begingroup\$ Determined by the rest of the circuit means exactly that. Without specifying the entire circuit for the transistor we can not determine \$V_{CE}\$...unless the transistor is in saturation. Roughly, if \$\beta I_B > I_C\$ then the transistor is in saturation and the voltage from collector to emitter is not less than \$V_{CEsat}\$. Give us a schematic if you want a better answer. \$\endgroup\$
    – Elliot Alderson
    Commented Jul 4, 2022 at 19:51
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    \$\begingroup\$ @coulombs Note that you often have to think twice when reading these. It is listed as the "Maximum-Minimum" value, that is, they guarantee that under every condition listed and every kind of process variation, the saturation voltage is never higher than the listed value. It may be lower for an individual transistor, and it typically is. They just don't care to specify it further. \$\endgroup\$
    – pipe
    Commented Jul 4, 2022 at 19:53
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    \$\begingroup\$ And just as a further clarification, when @pipe says "never higher than..." that means "never of greater magnitude than..." Negative and positive numbers, as illustrated in the OP's table, are sometimes given in a technical way using different signs for PNP vs NPN. \$\endgroup\$
    – jonk
    Commented Jul 4, 2022 at 19:58
  • \$\begingroup\$ @ElliotAlderson I've added a graph that shows the saturation region. My understanding is that saturation is the bounded region in the lower left, but that would make Vce < Vce(sat) when saturated \$\endgroup\$
    – coulombs
    Commented Jul 4, 2022 at 20:29

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