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I've been working with a project regarding an SRAM Controller in Verilog. As you can see, my controller should include those blocks. I've written some Verilog Code and right now I'm trying to test it, but I have two doubts mainly:

My professor told me that the address line should be 32 bit, exactly like the data that I should provide to the SRAM when it comes to write or read operation, but the SRAM module has the address declared with 10 bits. Can anyone explain me why? And where should I change the width of the address in the Verilog Code?

The other doubt is: since this is an AHB-lite interface, how can I tell the arbitration block what happens when I have both requests coming from the two slaves and it is executed the first one and then the second? Like, how can I tell to the second slave that it needs to wait for the first one?

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  • \$\begingroup\$ I think we can't know why your professor told you to use 32 address bits even if memory utilizes 10 bits. There may be valid reasons we could guess but we would not know which of all the guesses are correct. We also don't see the verilog code so we can't tell where to change the memory address bus width. For your last question, it depends how the bus interfaces want their arbitration. What signals does the interface have for arbitration? \$\endgroup\$
    – Justme
    Commented Nov 1, 2022 at 17:10
  • \$\begingroup\$ The AHB bus is a 32-bit bus, so it ought to have 32 bit addresses. You're mapping your 1024-element SRAM onto some of the 4 GiB memory space that the AHB bus can address so the situation seems perfectly fine to me - can you explain why you think the AHB width and the SRAM address width must be equal? \$\endgroup\$
    – nanofarad
    Commented Nov 1, 2022 at 17:17

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but the SRAM module has the address declared with 10 bits. Can anyone explain me why? And where should I change the width of the address in the Verilog Code?

The addressable size of the memory probably amounts to only 10 bits (2^10 or 1024 x 32bits for a total size of 32768 or 32kbits). If you wanted to address more than 32k, you'd need to stack more than one "page" of 32k memory and use a mux to select between them.

If you just want to use one page, then just truncate the bits above 10.

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The AHB bus has a 32-bit address space. So it can address up to 4 GB and that space can contain any combination of memories and I/O devices the system designer wants.

Most 32-bit systems don't fill up their 4 GB address space.

Yours has a 32 KB device in, accessed as 1,024 32-bit dwords by a 10-bit address. Its 10-bit address connects to the AHB's 10 low-order address bits.

The value on some or all of the remaining AHB address bits are checked by address decoding logic. When the required value is detected, the SRAM controller is enabled and will respond to AHB transactions. This has the effect of mapping the SRAM into one (or more) address range(s) within the 4 GB address map.

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