/*
* Do not change Module name
*/
module stimulus;
reg[4:0] A, B;
wire [9:0] Product;
reg clk, start;
booth_multiplier m1(A, B, Product, clk, start);
initial
$monitor($time, "A = %b, B = %b, Product = %b", A, B, Product);
initial
begin
clk = 1'b0;
start = 1'b1;
#1000 $finish;
end
always #50 clk = ~clk;
initial
begin
A = 9; B = 7;
end
endmodule
module booth_multiplier(A, B, Product, clk, start);
input signed [4:0] A, B;
output signed [9:0] Product;
input clk, start;
// Initialize internal signals
wire clr, ld, addsub, rsh, pld, done, incr;
wire [1:0] temp;
wire [2:0] count0;
// Add a $display statement to debug
initial $display("Booth Multiplier Simulation Start");
// ...
// Add more $display statements if needed
// Instances of submodules
data_path data1(clk, clr, ld, addsub, rsh, pld, done, count0, A, B, temp, Product, incr);
controller con1(clr, rsh, addsub, pld, ld, clk, count0, start, temp, done, incr);
always @(posedge clk)
$display("Booth Multiplier: A=%b, B=%b, Product=%b, clr=%b, ld=%b, addsub=%b, rsh=%b, pld=%b, done=%b, incr=%b",
A, B, Product, clr, ld, addsub, rsh, pld, done, incr);
always @(posedge clk)
$display("Booth Multiplier: count0=%b, temp=%b", count0, temp);
endmodule
module data_path(clk, clr, ld, addsub, rsh, pld, done, count1, A, B, temp, Product, incr);
input [4:0] A, B;
input clk, clr, ld, pld, rsh, done, incr;
output addsub;
wire [10:0] Acc, data_out;
output [1:0] temp;
output [2:0] count1;
output [9:0] Product;
wire [4:0] sum1, M;
PIPO1 p1(M, A, clk, ld, clr); // load multiplicand
PIPO1 p2(Acc[5:1], B, clk, ld, clr); // load multiplier
PIPO1 p3(Acc[10:6], sum1, clk, ld, clr); // accumulator
//d_ff d1(Acc[0], 0, clk, clr); // q0
counter c2(count1, incr, clr, clk);
add_sub as1(sum1, M, Acc[10:6], addsub);
right_shift r1(rsh, clr, clk, data_out, Acc, ld);
PIPO p4(Product, data_out[10:1], clk, pld, clr);
comparator c1(Acc[1:0], addsub, clk, clr);
endmodule
module controller(clr, Rsh, As, pld, ld, clk, count2, start, temp, Done, incr);
input clk, start;
input [2:0] count2;
input [1:0] temp;
output reg clr, Rsh, As, pld, ld, Done, incr;
reg [2:0] state;
parameter init = 3'b000, load = 3'b001, idle = 3'b010, Rshift = 3'b011, done = 3'b100;
always @(posedge clk)
begin
case (state)
init : if (start) state <= load; else state <= init;
load : state <= idle;
idle : state <= Rshift;
Rshift : #5 if (count2 > 5) state <= done;
else state <= idle;
done : state <= done;
endcase
end
always @(state)
begin
case (state)
init : begin clr <= 1; pld <= 0; ld <= 0; As <= 0; Done <= 0; Rsh <= 0; incr <= 0;
end
load : begin clr <= 0; pld <= 0; ld <= 1; As <= 0; Done <= 0; Rsh <= 0; incr <= 0;
end
idle : begin pld <= 0; clr <= 0; ld <= 0; Done <= 0; Rsh <= 0; incr <= 0;
if (temp == 2'b01) As <= 0; else if (temp == 2'b10) As <= 1;
end
Rshift : begin clr <= 0; pld <= 0; ld <= 0; As <= 0; Done <= 0; Rsh <= 1; incr <= 1; end
done : begin clr <= 0; pld <= 1; ld <= 0; As <= 0; Done <= 1; Rsh <= 0; incr <= 0; end
endcase
end
endmodule
//-----------------------------------------------------------------------------
// Blocks in architecture
module counter(count1, incr, clr, clk);
input incr, clr, clk;
output reg [2:0] count1;
always @(posedge clk)
begin
if (clr) count1 <= 3'b0;
else if (incr) count1 <= count1 + 3'b1;
end
endmodule
module add_sub(out, in1, in2, addsub);
input signed [4:0] in1, in2;
input addsub;
output reg signed [4:0] out;
always @(*)
begin
if (addsub == 0)
out <= in1 + in2;
else
out <= in1 - in2;
end
endmodule
module d_ff(d, q, clk, clr);
input d, clk, clr;
output reg q;
always @(posedge clk)
if (clr) q <= 0;
else q <= d;
endmodule
module right_shift(rsh, clr, clk, data_out, data_in,load);
input clk, clr, rsh, load;
input [10:0] data_in;
output reg [10:0] data_out;
always @(posedge clk)
begin
if (clr) data_out <= 0;
else if(load) data_out <= data_in;
else if (rsh)
begin
data_out <= {data_in[10], data_in[10:1]};
end
end
endmodule
module PIPO(data_out, data_in, clk, load, clr);
input [9:0] data_in;
input load, clk, clr;
output reg [9:0] data_out;
always @(posedge clk)
if(clr) data_out <= 0;
else if (load) data_out <= data_in[9:0];
endmodule
module PIPO1(data_out, data_in, clk, load, clr);
input [4:0] data_in;
input load, clk,clr;
output reg [4:0] data_out;
always @(posedge clk)
if(clr) data_out <= 0;
else if (load) data_out <= data_in;
endmodule
module comparator(in, as, clk, clr);
input [1:0] in;
output reg as;
input clk, clr;
always @(posedge clk or posedge clr)
if (clr)
as <= 0;
else if (in == 2'b01)
as <= 0;
else if (in == 2'b10)
as <= 1;
endmodule
output - Booth Multiplier: A=01001, B=00111, Product=xxxxxxxxxx, clr=x, ld=x, addsub=x, rsh=x, pld=x, done=x, incr=x
