Why am I getting error C:\Program Files (x86)\iverilog\bin\iverilog.exe: unknown option -- O when trying to run this Verilog code?

Question

On Visual Studio, I run this Verilog simulation command, but I get the error message:

iverilog -O hello_tb.vvp hello_tb.v 

error C:\Program Files (x86)\iverilog\bin\iverilog.exe: unknown option -- O

---

module hello(A,B);

    input A;
    output B;
    assign B = A;

endmodule


`timescale 1ns / 1ns

`include "hello.v"

module hello_tb;

    reg A;
    wire B;

    hello uut(A,B);

    initial begin
        $dumpfile("hello_tb.v");
        $dumpvars(0,hello_tb);

        A=0;
        #20;

        A=1;
        #20;

        A=0;
        #20;

        $display("test finished");        
    end
endmodule

Answer 1

-O is not a supported option for the iverilog command, as the error message clearly shows.

One way to see what options are supported is to use the -h option to get help for the command:

iverilog -h
Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]
                [-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012] [-g<feature>]
                [-D macro[=defn]] [-I includedir]
                [-M [mode=]depfile] [-m module]
                [-N file] [-o filename] [-p flag=value]
                [-s topmodule] [-t target] [-T min|typ|max]
                [-W class] [-y dir] [-Y suf] [-l file] source_file(s)

The option you are looking for is the -o option (lower case letter "o", not upper case "O").

Another way to find the supported options is to read the iverilog documentation.

---

There is another problem with your code:

    $dumpfile("hello_tb.v");

That will write out the VCD waveform file, clobbering your Verilog testbench file of the same name (hello_tb.v). It is conventionalt to use a .vcd file extension for VCD files. Use:

    $dumpfile("hello_tb.vcd");