How can I switch a high-side transistor from logic referenced to ground?

Question

Problem: I have a logic signal (represented by SW1), say from a microcontroller, that is either 0V or some low voltage, maybe 5V or 3.3V. I have a higher voltage supply (V1) and a switching device (M1) on the high side of that supply, connected to a load.

^{simulate this circuit – Schematic created using CircuitLab}

Sometimes, there is an H-bridge, or half an H-bridge, and I need to control the high-side transistor(s) (M2), but I think basically it's the same problem:

^{simulate this circuit}

The difficulty is that my logic output is only 0V or 5V, but I need higher voltages, like maybe 50V and 45V, to switch the high-side transistor. I understand that the precise voltages required will depend on the transistors I select -- I'm just wondering how to solve this problem, generally.

Is there a simple way to do this if my application is not very demanding? If I need to do the switching rapidly, say for a PWM application at 50kHz, is there a more complicated way to do it?

Answer 1

Aside from IC and isolated solutions (e.g. high side switch ICs, transformers, opto, etc - which is what you'd usually go for nowadays), one simple solution is a reasonably fast discrete PMOS driver circuit like this:

Obviously you can just use the one NPN version, but the push pull increases drive capability. This is just the rough idea, divider can be adjusted and protection added to ensure Vgs tolerance is met. Q1's emitter resistor is to prevent it saturating and lengthening the turn off time.

Simulation at 1MHz - I added the gate voltage (red trace), note it only swings ~7V, it follows the Q2/Q3 base voltage (a zener can be added as mentioned if needed):

Answer 2

How about a pull-up for the M1's gate (the P-FET) and an N-FET (M2) from that gate to ground? If you power M2 you pull M1's gate low, switching it on. If M2 is off the pull-up resistor ensures M1 is switched off.

More details: P-FET M1 is switched on if its gate becomes a few volts lower than the source (the arrow). ANd N-FET M2 is switched on if its gate becomes a few volts higher than the source. So if you apply a high voltage to M2's gate it will be on, pulling the gate of M1 low. This creates the required voltage drop between gate and source to switch M1 on. So applying a voltage to M2 will switch M1 on.
If you make the gate of M2 low it will switch off. Then the gate of M1 will be pulled high by R1, and there won't be a voltage difference between gate and source. Then M1 will switch off.

Answer 3

There are few basic solutions:

Gate transformer: you will be able to control both transistors in a leg with one transformer but the transformer itself may be hard to design.

Fully isolated gate drivers: simple but expensive solution as you will need to provide isolated power to high side gate driver(s). This means using expensive DC/DC converters or a transformer with multiple isolated secondary windings.

Bootstrap circuit: the boost capacitors provide power for high-side gate drivers. These caps are charged when low-side mosfet is on. This is a cheap solution but you must be sure to properly start-up the circuit. First turn-on all bottom mosfets to charge the boost caps. Only then can you properly start the converter.

Answer 4

If you don't need a very high switching speed, an optocoupler will do the trick. If the switching voltage is high, you might need a zener diode to make sure you don't exceed the Vgs spec for the FET.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 5

I'm going for the high power and fast PWM end of the question because its the most difficult to solve as a design. I deleted yesterday's answer not because it was wrong but because this is a more refined idea: -

After the schmitt trigger has restored the control waveforms I'd use a standard push-pull MOSFET driver and, due to the slight asymmetry in the rails it will produce (say) a 12V active drive to the gate with a 2V reverse drive for switching the gate off quickly.

I would use the same driver topology on both FETs so that any delays are equal to both top and bottom FETs.