I have to generate 2 5-bit random numbers and add them using structural verilog and implement it on FPGA. I have to design LFSR with 5 D flip flops and the 5-bit pseudo random number is given by the outputs of the flip-flops. The 5 flip-flops are connected in serial and the 5th flip-flop is xor-ed with the first.
This is the code I have written so far. I am new to verilog and electrical concepts.
module dff (Q, D, Clock);
output Q;
input D;
input reset;
input Clock;
reg Q;
always @(posedge Clock)
begin
if (reset)
Q = 1;
else
Q = D;
end
endmodule
module DFF_LFSR() ;
input D;
input clk;
input reset;
output Q1, Q2, Q3, Q4, Q5;
reg Q;
dff DFF1(Q1^Q5, D, reset, clk);
dff DFF2(Q2, Q1, reset, clk);
dff DFF3(Q3, Q2, reset, clk);
dff DFF4(Q4, Q3, reset, clk);
dff DFF5(Q5, Q4, reset, clk);
endmodule
dff DFF1(Q1^Q5, D, reset, clk);
is illegal. Run in a Verilog simulator. \$\endgroup\$