Johnson counter using structural modelling in Verilog

Question

I'm trying to build a 4-bit Johnson counter using JK flip flops and structural modelling. For the FF's themselves I'm using behavioral code and then instantiating them inside the counter module which is using structural style.

module jkff(input j, input k, input clk, input rs, output reg q, output reg qn);
    always@(posedge clk) begin
        if (rs) begin
            q=0;
            qn=1;
        end
        else begin
            q=(j&k)?~q:(j&~k)?1:(~j&k)?0:q;
            qn=~q;
        end
    end
endmodule

module johnson(input clk, input rs);
    wire q1, q2, q3, q4;
    wire qn1, qn2, qn3, qn4;
    jkff jkff1(qn4, q4, clk, rs, q1, qn1);
    jkff jkff2(q1, qn1, clk, rs, q2, qn2);
    jkff jkff3(q2, qn2, clk, rs, q3, qn3);
    jkff jkff4(q3, qn3, clk, rs, q4, qn4);
endmodule

module tb_johnson();
    reg clk;
    reg rs;
    johnson johnson1(clk, rs);
    initial begin
        #0 clk=0;
        #2 rs=1;
        #60 rs=0;
        #500 $finish;
    end
    always 
        #5 clk=~clk;
    initial begin
        $dumpfile("johnson.vcd");
        $dumpvars;        
    end
endmodule

The problem is in the output. I'm expecting each FF to go 1111000011110000 and so on, and for all FFs to be staggered by one clock pulse to the previous one. What I'm getting is:

. I can't find the issue, but I'm thinking it has to do either with reset logic or with my testbench itself. I have tried the same circuit with D FF's instead of JK and am facing the same problem.

Answer 1

Few observations:

• Use only nonblocking assignments to model sequential logic.
• In the JK Flip Flop, assign qn using a continuous assignment outside the sequential logic block e.g. use assign qn = ~q; so that it correctly reflects the complemented value of the current value of q (not the previous value). qn should represent the complement of q, so it should use combinational logic.
• Make the q and qn ports of the Johnson counter as outputs so that the Johnson counter can be used in other modules.