Can `ADD` create a control hazard while in the `MEM` stage?

Question

Imagine there is a machine that has shared memory for both data and instructions (which means a control hazard can occur between the MEM and IF stages). Can instructions such as ADD that do nothing during the MEM stage cause a control hazard with other instructions that are in the IF stage?

ADD $1, $1, $3 :       IF  ID  EX  MEM WB
SUB $4, $5, $6 :                   IF  ID  EX  MEM WB

In the example above, is there a control hazard between the MEM stage of the ADD instruction and the IF stage of the SUB instruction?

Edit: Description of the each instruction.

IF  - Instruction Fetch
ID  - Instruction Decode
EX  - Execute
MEM - Memory Access
WB  - Write-Back

Answer 1

The traditional RISC pipeline with separate Fetch and Mem states is generally tailored for separate instruction and data busses (aka "Harvard"), often connected to separate Instruction and Data caches. The purpose is being able to simultaneously do instruction fetches and data accesses, with a nice symmetry : IF for the instruction bus, MEM for the data bus.

If your RISC CPU has only one external bus, multiplexed for instructions and data, load or store instructions will stall the fetch part and incur a pipeline bubble, so that the instruction will cost 2 cycles. (An old example : Cypress 7C601)

Back to your question

A simple ADD instruction does nothing in the MEM stage, there is no control hazard with a subsequent SUB, or load, or store, or whatever. There may be data hazards, solved by stalling and/or bypassing, if the consecutive instructions use/depends on the same registers.

Answer 2

If the memory is a single port memory, i.e. you cant read and write (from/to different locations), IF generally can't occur during MEM phase. This problem can be addressed in several ways:

• build a dual port memory: that costs a lot but eradicates the problem
• bubble the pipeline: there's some more circuitry that determines if a control hazard can occur and insert some delays around to avoid that. That's somewhat costly and difficult do design
• you manually insert a lot of delay states in the pipeline. No "smart" circuitry needed, some registers are needed but it's really simple. Please note that in this way each instruction will require two memory accesses, IF and MEM, and that becomes a limit for speed.

In a RISC von Neumann architecture though the second option is probably the most used: the only two instructions that actually use the MEM status are load and sto so "bubbling" the pipeline should be, if not trivial, quite easy.