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I've been prototyping a circuit for a first year university engineering project and I've been running into some problems with one section of the circuit that has really stumped me.

Basically the flip flop and the decade counters I have are sometimes powering on with random values, not their default ones. As I understand it, the flip flop should start with Q = LOW and the decade counters should have Q0 = HIGH, but this happens only occasionally. I've tried putting a capacitor on the reset line that comes out of the right counter, connecting it to VCC, but that seems to freeze up the counter for some reason.

I'm not too experienced with ICs, so I'm not sure if I'm perhaps damaging them or trying to draw too much current out of them by using diodes. I'm also not sure if the pull-down resistors I have are important to have, or if I should have them on every chip. If anyone could explain what I'm doing wrong, or what can cause random values on power on, that would be really helpful, because I am completely stumped.

EDIT: Thank you to everyone for your help and answers to my problem. It seems that, with these specific chips at least, my assumption that they had a default power on state was incorrect, and that I need to implement a reset pulse that goes high when I first power on my circuit, by using a resistor and capacitor. Thanks again for all your support and advice.

enter image description here

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    \$\begingroup\$ What are their default values and where did you get that information? \$\endgroup\$ – David Oct 5 '14 at 16:57
  • \$\begingroup\$ From the theory we've done in lectures, it always seemed that the flip flop would start with Q = LOW and notQ = HIGH and that Q0 = HIGH on the decade counters. I haven't explicitly seen anywhere that they start way, is assuming that incorrect? I did try putting a sort of reset capacitor in the circuit but it seemed to cause more issues. \$\endgroup\$ – Adam Oct 5 '14 at 17:10
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    \$\begingroup\$ @adam This probably is just an assumption you get to make in the theory, because it makes further evaluation easier, but in the real world this state is only guaranteed by set or reset pins as described in the truth table. \$\endgroup\$ – Asmyldof Oct 5 '14 at 17:21
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    \$\begingroup\$ There are no power supply decoupling caps in your circuit, did you add them in the physical device? 100nF, short leads to the power supply pins of each IC and each IC its own cap. \$\endgroup\$ – jippie Oct 5 '14 at 18:23
  • \$\begingroup\$ @jippie What do the decoupling caps do? We haven't learnt about them. Is it to prevent chip damage? \$\endgroup\$ – Adam Oct 6 '14 at 20:09
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Your circuit needs to be started in a known state, and if the default is to be with the 4013's Q low and both 4017s' Q0s high, then to that end I've taken the liberty of redrawing your circuit, below, to include the Power-On-Reset using diodes to make it compatible with the rest of your diode logic.

Note that your R5 isn't needed since the diodes are being driven by a CMOS totem pole which never floats.

enter image description here Just for fun I've also added in some arbitrary clocks - to make it run - and, below, included a version of your circuit - with the same functionality but simplified by eliminating all the diodes and their associated resistors and replacing them with CD4071 OR gates. The LTspice files needed to play with the circuits or run simulations, if you want to, are here

enter image description here

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  • \$\begingroup\$ Thank you for your extremely useful answer! I learnt a lot reading it and I'll definitely implement your solution to my problem. \$\endgroup\$ – Adam Oct 6 '14 at 19:52
  • \$\begingroup\$ You're welcome; my pleasure! :-) \$\endgroup\$ – EM Fields Oct 6 '14 at 20:02
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This is normally solved by a dedicated /RESET pin on the IC that can be pulled low to bring the IC into a predictable and useful state.

This line is usually driven by the power supply for as long as the supply voltage isn't stable, and can be used again if the system goes into an invalid state.

This state need not necessarily have defined states for all flip-flops, it is sufficient to define a minimal initial state that allows you to reach every other state; e.g. a CPU would start execution at a specific address but with arbitrary register values, because the boot loader can simply overwrite the registers once it is running.

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I'm afraid your assumption is not entirely correct.

If a datasheet doesn't give a guaranteed initial state, which standard HEF40** device sheets intentionally don't, there is no guarantee.

The decade counters in fact hint at the fact that they start with the value you assume if, and only if, the master reset has been triggered.

The only thing you can assume about logic is what it says in the truth table, the rest is shooting in the dark unless very clearly stated otherwise in the logic's specific datasheet.

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You must assert Reset on power up. Create a signal and call it POR. (power ON reset)

It is customary to generate this with an R pull-down and C pullup to V+ to any CMOS input. Then use correct output polarity to feed all memory cells ( incl. FF) as required.

CMOS is usually positive Logic, so 1 for Reset requires a non-inverting reset gate. The RC time constant must be longer than the PS start-up time, such as 100ms.

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