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How do I obtain the falling delay driving by signal A:

Data:

NMOS W/L=1/.35

PMOS W/L=2/.35

Resistor-NMOS= 1/2 and PMOS5 Kohms.micro 

Cgate=Cdif=4/3fF/microm

Cmetal-ground=100fF

Cmetal-metal=39fF

Rmetal 800 ohms

1.-When B is not switching

2,-When B is switching simultaneously in the same direction than A

3.-When B is switching simultaneously opposite to A circuit delay

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  • \$\begingroup\$ Thank you Null, next time i will try to be more specific on the question. \$\endgroup\$
    – TechStudent
    Commented Oct 30, 2014 at 18:26

1 Answer 1

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If I understand correctly your aim is to have falling slope of inverters appear later than rising slope? If so, if it is available reduce W/L ratio of NMOS transistor and increase W/L ratio of PMOS transistor.

Capacitances on the output are seen both by NMOS and PMOS transistors.

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  • \$\begingroup\$ I am confused on the switching part the two inverter(A and B) are connected and each one has its own capacitance(Cmetal-ground=100fF and Cmetal-metal=39fF, i guess?). So the part where i am confuse is what formula should i need to applied when it is switching. Sorry i did not get this comment "reduce W/L ratio of NMOS transistor and increase W/L ratio of PMOS transistor." \$\endgroup\$
    – TechStudent
    Commented Oct 31, 2014 at 14:03
  • \$\begingroup\$ ​​ You have 4 cases when inverters switch their states: 1. inverters A and B switch from 0 to 1 at the same time 2. inverters A and B switch from 1 to 0 at the same time 3. inverter A switches from 0 to 1 and inverter B switches from 1 to 0 4. inverter A switches from 1 to 0 and inverter B switches from 0 to 1 In my opinion, for cases 1 and 2, capacitance Cmetal-metal should be seen as 39 fF so nothing special happens. For cases 3 and 4, capacitance Cmetal-metal is larger due to Miller phenomenon. So rising/falling edges are longer. Inverters need more time to go from 0 to 1 or from 1 to 0. \$\endgroup\$
    – Tako
    Commented Nov 3, 2014 at 14:42
  • \$\begingroup\$ I won't give you exact formula. Just use a simulator. The good thing is to now what is going to happen. For exact calculations use a simulator. "reduce W/L ratio of NMOS transistor and increase W/L ratio of PMOS transistor." Inverter is constructed from NMOS and PMOS transistors. To reduce W/L ratio means to reduce the width (called W) of a transistor or to increase its length (called L). To increase means the opposite - increase the width or reduce the length. \$\endgroup\$
    – Tako
    Commented Nov 3, 2014 at 14:42
  • \$\begingroup\$ I am working on it, thank you for your comments, it has been useful. \$\endgroup\$
    – TechStudent
    Commented Nov 4, 2014 at 18:50
  • \$\begingroup\$ @TechStudent No problem. Please notify if you succeed. \$\endgroup\$
    – Tako
    Commented Nov 5, 2014 at 8:28

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