First things first, is it even possible to scale up the frequency using only digital elements, atleast approximately? Though a frequency divider circuit can be designed very easily with flipflops. In the circuit I'm designing, there is no option left for me rather than doubling the input frequency. Any suggestions on how to proceed/design this circuit?
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2 Answers
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Doublers are possible using digital circuits, the following diagram is one such example. The trouble with it is that it relies on propagation delays in delay chains in order to generate the doubled frequency. This means that you don't get a guaranteed duty cycle, it will vary depending on how long your chain is. The clock will probably also be fairly jittery.
In fact, such a circuit would probably work as a frequency doubler even without the register - with just the input clock connected directly to the delay chain.
answered Apr 24, 2015 at 4:34
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\$\begingroup\$ You can correct the duty cycle by using a T-FF after your newly generated clock. Because a T-FF divides a clock by 2, you will need to multiply your original clock by 4. \$\endgroup\$– PaebbelsCommented Apr 24, 2015 at 6:11
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\$\begingroup\$ Though this isnt that accurate, it clearly solves my problem! \$\endgroup\$– vineel13Commented Apr 24, 2015 at 16:35
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Not really. You need some sort of analog circuitry to do this. A PLL is generally the proper solution in this case. The idea is to use a voltage controlled oscillator to generate a new frequency that has a precise mathematical relationship to the reference frequency. There are some other techniques that involve delays (possibly RC circuits or inverter chains) and XOR gates, but these are not always feasible or reliable. They also rely on the input clock duty cycle being very close to 50% and they may produce outputs with inconsistent or frequency dependent duty cycle.
answered Apr 24, 2015 at 4:01