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When I'm approaching a problem in C++ or python, there are many libraries that exist which do the heavy lifting of my code. I'm thinking about GNU GSL, BOOST, or FFTW for C++, and NumPy or SciPy for python. In many ways, the fact that these resources exist make coding in these respective languages worthwhile, as the libraries prevent you from having to rewrite all the low level things from scratch.

The IEEE standard libraries seem to cover only the very basics, such as data types (sort of akin to the C standard libs).

It seems like in VHDL, you can buy/find some "IP Cores" that will solve a problem, rather than using an open source library. In python, if I want to talk to a serial device, I just import serial and I'm basically done. In VHDL I would either be stuck writing a serial protocol from scratch, or I would have to google around on the various repositories until I found someone who had produced something that sort of works. I would then be patching bits of code into my project, rather than just including something and calling that. In a similar way, if I want to perform an FFT, I can find examples of FFTs in VHDL via google, but there is not something simple like FFTW that I can find.

Are there any comprehensive open source libraries available that I can import into my projects? Why does everyone seem to roll their own code for so many of the same things?

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    \$\begingroup\$ Have you searched opencores.org ? \$\endgroup\$ – MarkU May 1 '15 at 18:05
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    \$\begingroup\$ For VHDL verification libraries, see osvvm.org \$\endgroup\$ – Jim Lewis May 1 '15 at 19:28
  • \$\begingroup\$ Opencores, you can also buy libraries from various sources. You will spend some time with most cores from opencores as most are not documented well. \$\endgroup\$ – Voltage Spike Nov 17 '17 at 6:36
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I'm a developer and maintainer at 'The PoC Library'. We try to provide such a library composed of packages (collection of new types and functions) and modules. It comes with common fifos, arithmetics, cross-clock components, low-speed-I/O components and a Ethernet/IP/UDP stack (next release).

As @crgrace described, it's quite complicated to design modules, which:

  • work on many platforms
  • support most vendor tool chains
  • add no/less overhead

Our library has an internal configuration mechanismn (PoC.config) to distinguish vendors, devices and even device subfamilies to choose the right code or an optimized implementation. It also distinguishes between synthesis and simulation code at some points.

For example PoC.fifo_cc_got is a FIFO with an 'common clock' (cc) interface and put/got signals to control the fifo. The fifo is configurable in widths, depths, fill-state bits and implementation type. It's possible to choose a LUT-based RAM or On-Chip-RAM (ocram) implementation type. If this fifo is synthesized with ocram option for Altera, it uses altsyncram; if Xilinx is chosen, it uses a generic BlockRAM description and implements the pointer arithmetic by explicit carrychain instantiation (Xilinx XST does not find the optimal solution, so it's done manually).

There are 2 other fifo types with 'dependent clock' (dc) and independent clock (ic) interface. So if it's required to switch from an normal fifo to a cross-clock fifo (PoC.fifo_ic_got), change the entity name and add a clock and reset for the second clock domain, that's all.

I think this proves, it's possible to write common modules, which work on multiple platforms and compile in different tools (Spartan->Virtex, Cyclone -> Stratix; ISE, Vivado, Quartus).

Besides PoC, there are other open source libraries:


The "Discover Free and Open Source Silicon" (FOSSi) projects on GitHub offers a browsable database of all GitHub projects that mainly use , , , or any other important hardware description language ().

See also:

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  • \$\begingroup\$ +1 for showing what you've done and also what others have done. Good long list. \$\endgroup\$ – Mister Mystère Feb 9 '16 at 10:57
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Open source libraries like you describe wouldn't be as nearly as useful for VHDL or Verilog as they are for a general purpose programming language. This is because HOW you implement a given function can very a lot depending on what you're trying to do. Code that is good for and FPGA is probably not so good for an ASIC and vice versa.

Also, since we are describing hardware, a function that does a FFT would require such specifics as word width and clock and reset strategy that it would tie your hands and constrain your whole design. If you made the function very flexible, it would have enormous overhead.

Lastly, look at the size of your executable when you include a lot of libraries in C, for instance. There is a ton of bloat there. That doesn't matter for software development (most of the time) but matters a lot for FPGA and especially ASIC development. There is no sense synthesizing a bunch of overhead you don't need.

So the bottom line is there are no such libraries, and your current approach is sound.

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  • \$\begingroup\$ The alternative (IP) core generators also provide the Scylla and Chabydris risks of vendor lock in and resulting bloat. FPGA and ASIC capacities have grown large enough to support bloat, the issue then cost and testing, helped by bloat standardization (e.g. AMBA AXI4). The trade off Time To Market versus "overhead you don't need" already made by entire industries. System design using building blocks instead of hardware design, the latter the bailiwick of VHDL. \$\endgroup\$ – user8352 May 1 '15 at 21:07
  • \$\begingroup\$ Your third paragraph is fairly ignorant of how compilers and synthesis tools work - tools should be discarding the things not needed and the results not used, likely even moreso in a digital logic setting than in a high level language library, where there may be some local variables and memory allocations that are overhead of the library abstraction, especially if it is dynamically linked. \$\endgroup\$ – Chris Stratton Nov 17 '17 at 3:30
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VHDL and Verilog are descriptive languages and they describe hardware blocks. A serial driver in C++ might translate into a Serial IP in VHDL/Verilog.

opencores.org is the biggest open-source database to date.

To facilitate the process of searching, download and code browsing (via Github) you can use this modern interface:

http://freerangefactory.org/cores.html

If, for instance, you search for serial you can end up here:

http://freerangefactory.org/cores/communication_controller/serial_uart_2/index.html

and directly jump to the code in GitHub. There you will see that you can quite easily instantiate the serial module and connect your own circuit to it and start sending and receiving data. This is as simple as serial libs in C++.

I hope this helps.

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The first site I go to for this kind of thing (as @MarkU mentioned) is opencores.org.

For example, there is a parameterized FFT engine, written in VHDL, released under the BSD license. Status is "beta".

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  • \$\begingroup\$ that's not what the OP ask. He or she knows about looking at opencores.org A parameterized FFT engine is a far cry from importing a standard math library in Python and using it. There is no such thing as "middleware" in hardware because of the overhead. \$\endgroup\$ – crgrace May 1 '15 at 18:31
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For Verification, there is Open Source VHDL Verification Methodology (OSVVM).
OSVVM is a comprehensive, advanced VHDL verification methodology that simplifies implementation of functional coverage, constrained random, and Intelligent Coverage Randomization (an intelligent testbench methodology). It also facilitates implementation of shared transcript files, error reporting, logs (conditional printing), and memory modeling.

OSVVM's website and blog are at http://osvvm.org. The packages are also available on github at: https://github.com/JimLewis/OSVVM

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