I am trying to design an image processing system on an FPGA to do Canny Edge Detection. The design is shown in the image below.
I have a large block ram to store my image. then i have smaller line buffers to read only the lines i am processing. I have 3 lines in use at a time ( with 1 other line as a pre-fetch for the next row of processing ).
The challenge I am having is that filter 1 looks at a 9 pixel box and outputs a value for the center pixel. so for a 10x10 image, the filter only outputs data for 8x8 pixels in the middle.
Once filter 1 has finished 3 rows, i want filter 2 to start on the modified pixel values. To pipeline this design, i am having a hard time figuring out how to deal with the 'missing' pixels that filter 1 does not output. what would be the best way to load those for Filter 2? should i have a way to bypass the first+last row and first and last pixel of each other other to my 2nd line buffer? or is there some other way i can do this?