As an experienced engineer (3 years with FPGA design and embedded systems), I'm telling you that you need to check the FPGA's datasheet and user guide. Its not a simple answer.
You have to make your design FITs the FPGA type you chose.
Some FPGAs have FlipFlops that were designed for Async reset, some are designed for Sync reset.
You have to check the FPGA user guide for what type of FlipFlops you have.
The Implementor/Mapper will chose dedicated routes for your reset (code can run at higher freq and takes less space) if you match your code with the FPGA primitives type.
Your design will work in ANY case, but sometimes the FPGA Implementor will go out of its way to make your logic work (adds more logic), but that will cause lower maximum frequency and/or more FPGA ressources.
Example: tested with Xilinx's ZYNQ (FPGA is designed for synched reset - see primitives user guide). By changing reset from async to sync, max stable frequency went from 220MHz to 258MHz and so I passed my frequency margin.
Also I might add that the Implementor does not know what is a clock and reset signal. It assigns flipflop pins to signals by ORDER, not by name. So in some FPGAs, the implementor choses the first signal after "process() begin" in VHDL as the clock, in some as the reset, depending on what FPGA the implementor is set to.