does a 2-flip-flop synchronizer for clock domain crossing need a clear (reset) input signal?

Question

In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device.

Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing purposes to pass signals to slower clock domain.

Since most of the resets in my design are driven as synchronous resets, every time I run timing validation the tool shows it failing at the reset stage.

I was wondering if I could use the 2-flip-flop synchronizers without reset. From what I've found so far, that seems to be the case.

Answer 1

The synchronizer doesn't need a reset to perform its synchronization function.

However, if it is important at system startup to avoid unintended signals then a reset will be needed.

Of course, if implementing the logic in an FPGA you may want to initialize the registers just to avoid the first few clock pulses being unknown in the simulation. Depending upon the logic the whole simulation could be "unknown".