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Let's say you unassert an asynchronous reset signal to a flip flop after you need to to meet setup timing but before the positive edge of the clock. You're in trouble right?

Now let's say you've got a chip full of thousands and thousands of flip flops, all asynchronously reset from the same signal. You unassert it right before the positive clock edge just by chance. Some interconnect delays are longer than others so when you deassert it, it'll reach one flop on time to clock in the D input but won't make it to another one on time. The whole point of the reset was to put the circuit in a known state, which it is while the reset is asserted but just due to bad luck parts of your circuit are off to the races where others are either waiting for the next cycle or went metastable.

What is commonly done to avoid this?

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  • \$\begingroup\$ The short answer is synchronous reset. If you are stuck using asynchronous reset, it should be asserted over multiple clock cycles. \$\endgroup\$ – Caleb Reister Sep 20 '19 at 1:17
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  • While assertion of an Asynchronous Reset is not an issue, de-assertion can be an issue if it happens near clock edge. Asynchronous signals like Asynchronous Resets hence have to satisfy two timing checks to avoid metastability: Recovery and Removal checks . This is similar to setup and hold checks.

  • To avoid metastability condition, de-assertion of Asynchronous Resets are normally made synchronous in designs and the design is then timing verified for Recovery and Removal Timing checks.

reset synchroniser with active low async reset and synchronised de-assertion:

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Just like clock, reset is also a high fanout signal and hence it has to be properly distributed through out the design with buffers.

  • Asynchronous Resets are also prone to spurious resetting due to glitches in the line. Hence some glitch-filtering mechanism is also incorporated on this line.
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Controlling a reset that way is no more different then controlling the clock. The clock also has to arrive nearly simultaneously at all registers. Therefore you build a clock-tree which is highly tuned.

Thus a solution is to build a reset tree which meets the reset timing requirements, just like you have to build a clock tree. In contrast to a clock tree where you might use positive and negative edges, the reset tree is normally tuned only for the release of the reset. Therefore a reset input often has a minimum pulse width.

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The solution is obvious. If you use an asynchronous reset, then you absolutely do not deassert it "right before" the clock edge. Ever. You design the system so that you never violate the flip-flop setup time under worst case conditions including wiring delays.

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