Let's say you unassert an asynchronous reset signal to a flip flop after you need to to meet setup timing but before the positive edge of the clock. You're in trouble right?
Now let's say you've got a chip full of thousands and thousands of flip flops, all asynchronously reset from the same signal. You unassert it right before the positive clock edge just by chance. Some interconnect delays are longer than others so when you deassert it, it'll reach one flop on time to clock in the D input but won't make it to another one on time. The whole point of the reset was to put the circuit in a known state, which it is while the reset is asserted but just due to bad luck parts of your circuit are off to the races where others are either waiting for the next cycle or went metastable.
What is commonly done to avoid this?