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I created an FPGA system on ModelSim (a simple algorithm that calculate an equation and save on-chip), synthesized with Quartus Prime, then downloaded to my DE1-SOC.

My intention is to compare my results with an implementation made in a paper. In the paper they make almost the same calculation than me, and they report speeds around 15 "ms" mili-seconds. They don't provide frecuency speed about their system but about the NIOS-II processor itself which is 75 Ghz.

In my system I'm not using NIOS-II, but rather calling altera IP's for Mul,Div etc.

Now, I don't know exactly how to read my own speed values. Here in this forum I was told that I should look at the compilation report of Quartus Prime, exactly what segment of the compilation report should I look at?

Looking at the wave in the modelsim, tracking when it finish the calculation it says it is completed on terms of "PS" Pico-seconds and the conversion to "ms" I'd have less than 1 milisecond. So it means my system is faster than the aforementioned paper?

Exactly which department should I see in the compilation report of modelsim to know the Speed of my system aka calculation time.

This values come from softwares, are these values exactly the same that what is physically happening in the board itself?

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    \$\begingroup\$ Firstly, you know the NIOS-II is not 75 GHz. Secondly, the timing analysis from the finished FPGA design will tell you the maximum supported clock rate. Then from Modelsim you'll know the number of clock cycles your algorithm takes. Combining tose two parameters will give you the speed. \$\endgroup\$
    – user16324
    Commented Feb 6, 2017 at 9:56
  • \$\begingroup\$ @BrianDrummond my timming analysis report says: Slow 1100Mv 85c report / Fmax 4.99 Mhz, Restricted Fmax 4.99 Mhz, Clock Name CLOCK_50. Clock_50 is the clock that feed my entire system. So, the speed of my system is 4.99 Mhz? \$\endgroup\$
    – sujeto1
    Commented Feb 7, 2017 at 9:20
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    \$\begingroup\$ No, your clock speed has to be below 4.99 MHz. Your system speed also depends on the number of clock cycles required. \$\endgroup\$
    – user16324
    Commented Feb 7, 2017 at 12:02
  • \$\begingroup\$ So, the speed system equation should be something like CLOCK_50 (from quartus)* 0.18139272 ms (reading from Modelsim)? \$\endgroup\$
    – sujeto1
    Commented Feb 8, 2017 at 9:18
  • \$\begingroup\$ No. If you try to clock a 5MHz circuit at 50MHz it simply won't work. And you still haven't provided any information about the number of clock cycles you need to complete the operation. \$\endgroup\$
    – user16324
    Commented Feb 8, 2017 at 11:32

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First, you need to figure out the maximum allowed clocking for both designs (constrained by gates setup/hold-times, propagation delay etc). This will depend on the physical layout on chip (Quartus usually does a good job at this) and on your design, especially on the depth of logic that you put at the input of registers. More logic needs more time to settle and the register needs a settled signal before the next clock edge.

Use Quartus TimeQuest to find that value (it may run with every compilation depending on what task you choose in Quartus). BTW: Modeling the timing of chip-external connections is a bit of a black magic, it also depends on physical properties of the signaling and you should ignore it for a start. You may want to set the Modelsim clock to this value, so your time axis gives realistic readings.

The next question is about throughput: how many clock cycles does it take to process a certain amount of data. The NIOS-II will probably need hundreds of cycles to process one chunk of data while your design may accept one chunk per cycle. The cycle counts must be weighed by the clock speed of course (but again, chances are that your design is able to run at higher speed).

A different but related question is the latency of the computation. How long does it take to yield a result after giving input. Note that you may trade clock speed against latency by inserting registers in your design. This is called pipelining.

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  • \$\begingroup\$ In the compilation report - TimeQuest Analyzer, I have an Slow 1100Mv 85c report which says Fmax 4.99 Mhz, Restricted Fmax 4.99 Mhz, Clock Name CLOCK_50, also say another clock named: altera_reserved_tck with 53.73 Mhz, which one is the speed of my system? \$\endgroup\$
    – sujeto1
    Commented Feb 7, 2017 at 8:19
  • \$\begingroup\$ My sdc file is a very basic one, because I'm very new at this, I wrote like this ***create_clock -period 20.000ns [get_ports CLOCK_50] ***derive_pll_clocks ***derive_clock_uncertainty \$\endgroup\$
    – sujeto1
    Commented Feb 7, 2017 at 8:21
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    \$\begingroup\$ @sujeto1 4.99 MHz is pretty low for a CycloneIV. You need to learn how to find the critical path with TimeQuest. If you follow good design practices, you usually do not end up with such a low Fmax. Is there a feedback loop in a logic cone? \$\endgroup\$
    – Andreas
    Commented Feb 7, 2017 at 19:13
  • \$\begingroup\$ Thanks for answering, my FPGA is Cyclone V, can you confirm whether CLOCK_50 is the actual speed of my entire design? Since I have such of few experience on this I'm not sure how to do the "critical path with TimeQuest", is there a straigthfoward way to add a simple command in the SDC to solve this? What do you mean "Feedback loop"? my design run in a FSM and a lot of registers. \$\endgroup\$
    – sujeto1
    Commented Feb 8, 2017 at 2:31
  • \$\begingroup\$ @sujeto1 CLOCK_50 is the signal name for the boards 50MHz crystal oscillator (given in the sdc that is generated by the Terasic Tools). This will always be 50MHz (unless your board features a clock divider which I do not know). If your design violates timing constraints at 50MHz, you are responsible to generate a clock. This is done easiest with an onchip PLL. \$\endgroup\$
    – Andreas
    Commented Feb 8, 2017 at 17:45

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