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Been trying to access the FLASH memory on this DE1 dev board, but having no luck. I'm using this to interface with a Super Nintendo system, and I'm trying to read a small test ROM file stored on the FLASH. I've verified that the contents are good by dumping them back to a file and tested it.

I've written some basic VHDL to do this, but I think I'm missing something with the data bus end of it. I've done basic address line controls with CPLD chips before using VHDL, but never tried with a data bus.

Here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mapper_test is
port( 
FL_ADDR     : out   std_logic_vector(21 downto 0);
FL_DQ       : in    std_logic_vector(7 downto 0);
FL_CE_N     : out   std_logic;
FL_OE_N     : out   std_logic;
FL_RST_N    : out   std_logic;  
FL_WE_N     : out   std_logic; 

SNES_ADDR   : in    std_logic_vector(21 downto 0);       -- SNES ADDRESS BUS
SNES_DATA   : out   std_logic_vector(7 downto 0);        -- SNES DATA BUS
SNES_ROMSEL : in    std_logic;                           -- /ROMSEL (CART PIN 49)
--SNES_RST  : in    std_logic;                           -- CART RESET
--SNES_VCC    : in    std_logic;                         -- CART VCC
SNES_RD     : in    std_logic                            -- SNES /RD

);

end mapper_test;

architecture arch of mapper_test is

begin

--FLASH CONTROL PINS
FL_CE_N  <= SNES_ROMSEL;                                -- INPUT SNES /ROMSEL TO OUTPUT FLASH /CE
FL_OE_N  <= SNES_RD;                                    -- INPUT SNES /RD TO OUTPUT FLASH /OE
FL_RST_N <= '1';                                        -- KEEP FLASH /RST HIGH
FL_WE_N  <= '1';                                        -- KEEP FLASH /WE HIGH

--FLASH DATA PINS

SNES_DATA(7 downto 0) <= FL_DQ(7 downto 0);             -- INPUT FLASH DATA BUS (7:0) TO OUTPUT SNES DATA BUS (7:0) FOR READ MODE

--ADDRESS PINS
FL_ADDR(14 downto 0)  <= SNES_ADDR(14 downto 0);        -- INPUT SNES ADDRESS (14:0) TO OUTPUT FLASH ADDRESS (14:0) 
FL_ADDR(20 downto 15) <= SNES_ADDR(21 downto 16);       -- LOROM CONFIG ---> INPUT SNES ADDRESS (21:16) TO OUTPUT FLASH ADDRESS (20:15)
FL_ADDR(21) <= '0';                                     -- KEEP FLASH(21) LOW FOR 2MBYTE ONLY


end arch;

When I jumper the GPIO wires (all SNES ins and outs in code) over to my test cartridge, I get nothing but a black screen. I've even tried tying my LEDs to the FL_DQ pins to see if there is any activity, and there is none. So it seems to me like the data bus isn't going through properly. I just want to connect the FLASH to the SNES pins, nothing fancy at this point.

Can anyone tell me what I'm doing wrong?

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  • 1
    \$\begingroup\$ 1) Do you have any level-shifting hardware in place? The SNES is a 5V device, and your FPGA is probably 3.3V (or even lower). 2) What sort of flash device are the FL_ pins connected to? \$\endgroup\$ – duskwuff Feb 7 '17 at 0:15
  • \$\begingroup\$ It's just for testing so I haven't added any level shifters. I'm just using what's on the dev board. And the flash is a Spansion 29GL032N in 8-bit mode. \$\endgroup\$ – mikerakesh Feb 7 '17 at 1:37
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Fixed it.

Didn't have the Data pins set to 'Z' when not being accessed.

SNES_DATA <= FL_DQ when (SNES_ROMSEL = '0') else "ZZZZZZZZ";

That works properly.

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