I have used many decoupling capacitors in circuits and have seen them in many textbooks, but they never give an explanation about why they picked a certain size of capacitor. Everyone seems to have a "rule" about the size that they picked up along the way.

But is there an actual formula that dictates what size of decoupling capacitor to use? If not, are there some mathematics and physics that I could be pointed to to develop something more rigorous than a rule of thumb?

Many people have said that the size is not always critical, but I imagine there is a point at which changing the size would cause the circuit to fail or at least degrade. I would like to know what this critical point is, determining the bare minimum case, etc.

  • \$\begingroup\$ See also: electronics.stackexchange.com/questions/298798/… It's not a list of equations but it explains what is going on. \$\endgroup\$ – Joren Vaes Jun 14 '17 at 18:08
  • \$\begingroup\$ We used to have a guy around who linked out to a wizard of sorts, and it told you all the caps you needed to use. Can't find reference to it. Maybe someone can refresh my memory -- but the point is, if there's a wizard, a set of equations has been implemented. \$\endgroup\$ – Scott Seidman Jun 14 '17 at 18:12
  • \$\begingroup\$ Just to clarify, I am not asking about what size of cap to use in decoupling. I am asking how to determine the size without just using a rule of thumb. \$\endgroup\$ – royalt213 Jun 14 '17 at 18:24
  • 1
    \$\begingroup\$ Don't forget to consider package size intersil.com/content/dam/Intersil/documents/an13/an1325.pdf \$\endgroup\$ – DavidG25 Jun 14 '17 at 18:52
  • 1
    \$\begingroup\$ I answered this somewhat at electronics.stackexchange.com/a/274356/4512. \$\endgroup\$ – Olin Lathrop Jun 14 '17 at 19:57

Remember decoupling has several purposes.

  • On a load which draws transient, spiky currents like a CPU, decoupling caps store energy locally and close to the load, so it is available quickly (ie, with low inductance). The idea is that on each clock cycle, the cpu will gobble up a certain amount of charge (coulombs), which means the caps must both have large enough value and low enough inductance to provide needed charge without letting voltage sag out of its specified allowable range.

  • This brings us to their second role, which is to close high di/dt loops locally. This is needed to make the circuit work, as too much inductance will result in supply sagging, but it is also very beneficial, as it avoids injecting HF currents into the GND plane. Our CPU draws very fast currents, thus local, low inductance caps will be the first to respond. They then average out the current drawn from the larger, slower, higher inductance, and further away bulk caps. These in turn must provide charge while the usually slow regulator responds.

  • Same for the input of a buck regulator. It draws a fast square wave current, and the input decoupling caps' role is to make it flow in a tight local loop, and only draw a much less noisy, averaged current from the main supply.

  • On analog stuff like opamps, decoupling caps also filter out HF noise on the supplies. If your opamp goes into class B, slews, or draws a current spike as it wrangles a capacitive load, it will draws a distorted current or a current spike, which will inject distortion into the supplies. The resulting distortion at the output depends on supply impedance and PSRR at the relevant frequency.

  • And on the supply side, obviously the caps should make your regulator happy! Check its datasheet. Not all "stable with 1µF ceramic" LDOs are equal. Some have admirable transient responses. Others are horrendous. Same if there is a ferrite bead in the supply. Don't make a LC tank that resonates at a frequency you use...

Excess inductance in supply lines causes voltage sag on transient current demands. Digital stuff reacts to this by crashing, computing incorrect values, triggering UVLO or brownout detectors, and all kinds of fun stuff. Opamps and analog bits react by oscillating, taking forever to settle, increasing distortion, etc.

Excess inductance will also cause voltage spikes (positive or negative) when forcing large currents into it, as occurs on switching of a DC-DC converter. This will blow your FETs, your FET drivers... I've seen it several times on this website already.

Now, it's a bit involved and there are several approaches.

  • The Hobbyist

You like soldering 0805 because 0603 is to small. Being aware that inductance depends on package size and not value, you purchase a few hundreds of the largest caps you can get in 0805, probably 1-10 µF depending on voltage, and get a nice quantity discount. They you stick one on each power pin, without worrying, and it just works. You could put 100nF, but the price isn't that different for a hobbyist, and honestly, better put a cap which is 5c more expensive than actually think about the value you need, eh? I mean, if you value your time, spending 5c to save an extra minute thinking about the value you actually need is a no-brainer. Just like spending 50€ for chinese 4 layer boards versus slaving for two weekends painstakingly fitting the damn mess on two layers? Heck yeah.

Adding a 10c electrolytic will also save you the pain of debugging an oscillating regulator sometimes, a worthy investment when you make only a few boards.

Note: parallelling 100nF with 1µF is only useful if the 100nF is much smaller. If they're the same package, they got the same inductance. The smaller cap is only gonna be faster if it is smaller physically, and closer to the pins/planes.

  • The RF engineer

This guy has a good idea of the supply impedance he needs, and creates it by sticking various caps in parallel, taking into account package and via inductance, the fact that C0G works better at HF, perhaps exploit the self-resonant frequencies, make sure the supply doesn't resonate on the wrong frequency, stick a ferrite bead or two in the mix to add some filtering, etc. Here, impedance is more important than capacitor value.

  • The audiophile

He does basically the opposite, X7R SMD cap is about 1nH, thru-hole WIMA red boxes with 5.08mm pin spacing are about 6-8 nH mounted, and thus the HF noise on the rails is multiplied by the same factor, but who cares, it looks good! Also, the unstable LDO makes the treble fizzle, for that little extra something.

  • The baddass motherboard guy

In this case the manufacturer gives a recommended impedance profile for their chip's supply. And a software tool to make it easier. The result usually involves tons of low-value caps, because they have to be tiny, low ESL and fit between BGA vias or the like. Then he'll stagger values to get his impedance profile, check the thing with a VNA (under rated voltage). Then the cost-cutters will depopulate half the caps, of course.

  • The analog guy

Get an opamp with "100ns settling time to 0.1%". Stick it on a board with decoupling caps like 10nF//1µF. Every time it slews and draws a current spike, a LC resonance occurs between the two caps, overcomes the opamp's PSRR which is low at this frequency, and the settling time becomes 100x longer than it should. Solution is to use only ONE low-ESR cap, which will be ceramic, so it will be the small and local one. And use caps with actual ESR for the larger ones, which will dampen the impedance and not resonate. Like tantalums or electrolytics.

Rememeber your chip has very very thin bondwires, so it has like 0.1-0.5 ohm in the supplies anyway, so your opamp doesn't need, or care about the fact that the MLCC cap has 0.01 ohms ESR! This kind of ultra low ESR is a pain in the ... because of resonances.

Actually low ESR ceramics are such a pain, that some people like SUN came up with insane ways to stick some printed annular ring resistors on the internal layers to add some ESR!

Now they're starting to make "controlled ESR" ones. About time.

Note that I'm not talking about values a lot. The RF guy and the motherboard guy have an impedance target to meet, so it's more about how many caps, inductance, how to choose the staggered values, what type of caps to use, for the lowest cost. The analog guy will most likely use a small ceramic cap to make sure his opamp has a nice low inductance supply, and pick a value that fits in the package he needs...

  • 1
    \$\begingroup\$ Nice! I like your info and your attitude :) \$\endgroup\$ – bitsmack Jun 14 '17 at 20:57
  • \$\begingroup\$ "parallelling 100nF with 1µF is only useful if the 100nF is much smaller." Is this true? I thought that there was benefit to having different resonances and bandwidths by changing C (against a fixed L). Now that I say that, I realize it's a bit "hand-wavey"... \$\endgroup\$ – bitsmack Jun 14 '17 at 21:10
  • \$\begingroup\$ Only the RF guy could answer this ;) (I'm not into RF). Honestly the only use for low value MLCC is cost, or lower ESL due to smaller package. If you're a hobbyist, a strip of 1µF 0805 is an attractive proposition! If you parallel 2 caps, two of the same value will not have an antiresonance peak. 100nF+1µF will peak. \$\endgroup\$ – bobflux Jun 14 '17 at 21:34
  • \$\begingroup\$ Hello and thank you for your answer. I ask that you please keep in mind that many of us are crazy enough to jump into topics that we have little background on. So when you use phrase like "di/dt loops" or other less common acronyms, please add some text to indicate what you're talking about in a way that's reasonably searchable. Obviously, we can't find and create links for every concept we touch on, but I've done a lot of googling and not finding a definition for these values. di = direct amperage over dt = direct time? Dingle Amperage? Distance Incisors? :) \$\endgroup\$ – Daniel Santos Nov 18 '19 at 5:10
  • \$\begingroup\$ "Being aware that inductance depends on package size and not value" -- So you're saying that size does matter? :) \$\endgroup\$ – Daniel Santos Nov 18 '19 at 5:11

The main guideline is to maintain an adequate voltage at all the power pins at all times. This is usually all that's needed for digital circuits. In analogue circuits, the power rail can often act as an unwanted signal path, so there is a further requirement to have a wideband low impedance on the power rail.

If the circuit draws surges with time constants of uS to mS, then the board will often have a 100uF or so 'bulk' capacitor where the power comes into the board, to combat the output impedance of the power supply. If the main power supply is a simple mains rectifier, then much larger capacitors would be used here.

A digital circuit will take very large currents at transitions, but these will only last for nS. These are handled by a ceramic cap close to every power pin of every device. As the current pulses are so short, they are often in the 10nF to 100nF range.

More demanding applications can be handled by adding further capacitors, or ferrite beads or inductors to increase the isolation between different parts of the power rail.

  • 1
    \$\begingroup\$ Thanks, but I think you missed the point. I am not asking about what size of decoupling caps to to use in what situations or even how decoupling caps work. I am asking about how these numbers were arrived at. Everyone seems to have a rule of thumb without an explanation as to why that particular number was chosen. \$\endgroup\$ – royalt213 Jun 14 '17 at 18:26
  • 1
    \$\begingroup\$ @royalt213 The rule is obvious. Once you have the miniumum voltage, the pulse duration, and the pulse current, you use \$CV=Qdt\$. The problem is finding good values for the pulse currents and durations. That's why people tend to use default vaues. \$\endgroup\$ – Neil_UK Jun 14 '17 at 20:19

I have never seen an actual formula, more a gut feeling thing you gain from experience. Sometimes spec sheets will define a recommended decoupling amount, but it really depends on how busy the device it is associated with is.

If it is some quiet gate that monitors some user input or something then a small cap is fine. If it's a chip with lots of outputs all switching at clock frequencies with large fan-outs, you need a LOT more decoupling.

More often than not though it is dictated by the fact that your company purchases a specific size by the bucket load, so you routinely go with those.


Find or estimate the amount of the max current and max time that the load will take its 'excursion' from the nominal value of the voltage rail.

You can then use this formula to determine the relationship between the capacitor size and the amount of deviation from the nominal value of your power rail:

$$C=I\frac{\Delta T}{\Delta V}$$ Where I is the current, t is the time of the event and V is the difference in voltage away from the rail.

For example, if I had a load that drew 100mA more than average for 5us, and I wanted the rail to stay within 0.03V the equation would look like this:

$$C=100mA\frac{5us}{0.03V}= 17uF$$

or round it to 20uF to be better.

This works assuming 'step input' kind of current, if you had a sine wave you'd probably want to use a power factor to 'derate' the current. Use the equation to get you in the ballpark and then check the ripple and tune it in if necessary.

  • \$\begingroup\$ Interesting. It seems so simple like that. So then, hypothetically, would it be reasonable to take empirical measurements of noise on the signal and then use those variations in this formula to derive the proper capacitor to filter that noise? It seems like it could get complicated when the noise is random. But I suppose you could take the measurements that maximize the value of C perhaps? \$\endgroup\$ – royalt213 Jun 14 '17 at 18:32
  • \$\begingroup\$ 5uS is WAY more than just your normal decoupling though. \$\endgroup\$ – Trevor_G Jun 14 '17 at 18:34
  • 1
    \$\begingroup\$ And that formula takes no account for power supply recovery time. \$\endgroup\$ – Trevor_G Jun 14 '17 at 18:39
  • \$\begingroup\$ This seems like a good heuristic, but I would be mindful of the non-ideal properties of the capacitor used when using it for decoupling of a sensitive circuit since its decoupling efficiency will be different across the bandwidth of the circuit in question. This calculator will show what I am talking about graphically. app.pdntool.com \$\endgroup\$ – Luke Gary Jun 14 '17 at 19:03
  • \$\begingroup\$ What I'm saying is if you know something about your load (like max current draw) then you can size the capacitor for the duration and amount of filtering you require. \$\endgroup\$ – Voltage Spike Jun 14 '17 at 20:14

You can derive formulas for capacitors that allow a certain localised ripple voltage for a given localised chip current whilst being fed from a certain power rail having so many micro or nano henries in the power feed. You can extend this to accommodate other localised chips and possibly make decisions about sharing a decoupler. Then you have to think about the self resonant frequency of some capacitors and decide if in fact lower values are more preferable or maybe two capacitors of differing resonant frequency might be most appropriate. You might also want to factor in the effective series resistance of some capacitors typically electrolytic and do a whole load of math.

On the other hand, you take the practical approach and typically choose 100 nF for your digital chips and if you think the speed is high enough choose a 10 nF to avoid resonance. You should also read each chip's data sheet and see what it recommends.


Not the answer you're looking for? Browse other questions tagged or ask your own question.