I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next cycle. I have attached an image of the design that I am doing. How can I define the timing constraints on my design on FPGA ? I put clock constraints for 100 MHz and 25 MHz in my design on FPGA. Now the problem is, both the FPGA and the DAC chips sit at some unknown distance on Virtex-4 evaluation board. So how to make sure that the timing is met there, when the routing delay is unknown along the path ? What should be the input/output delay constraints?
At 25Mhz board delays are probably largely irrelevant (It is the sort of thing you worry about with multi hundred MHz memory clocks).
First thing I would do is to make sure that the output from the user logic is registered by that 25MHz clock so as to ensure you have defined timing at that point, then define constraints for the data relative to the 25MHz launch clock by studying the DAC datasheet for the setup and hold timings, you can afford to be a bit conservative here as everything is running so slowly.