I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. Still, when I have to code them in a sdc file I can't get through it. I have to spend several days trying and failing to make the Quartus software accept my design. And I know for sure that many other FPGA designers are suffering like me.
Somebody please stop this agony!
Let's try with an example. Consider the following top entity:
entity top is generic ( W : positive := 8 ) port ( ser_data_in : in std_logic; -- Serial data in ser_bclk_in : in std_logic; -- Bit clock in ser_fclk_in : in std_logic; -- Frame clock in par_data_in : in std_logic_vector(W-1 downto 0); -- Parallel data in par_wclk_in : in std_logic; -- Word clock in ser_data_out : out std_logic; -- Serial data out ser_bclk_out : out std_logic; -- Bit clock out ser_fclk_out : out std_logic; -- Frame clock out par_data_out : out std_logic_vector(W-1 downto 0); -- Parallel data out par_wclk_out : out std_logic -- Word clock out ); end entity;
Serial data is transmitted at DDR, clocked by the bit clock (frequency = F), which is center-aligned. Serial data comes also with a frame clock, which is edge-aligned with the first serial bit (frequency = F/W). Parallel data is SDR, clocked by the word clock (frequency = F/W), which is edge-aligned.
I won't enter into SERDES details, let's imagine that I have a simple shift register that shifts with ser_bclk_in and transfers its data to another register every rising edge of ser_fclk_in. Deserialized data operates somehow with parallel input data and the result is output to ser_data_out and par_data_out. Naturally, the SERDES at the output is specular to the input.
My question is: for a given maximum skew between data and clocks, how do I constrain such a design? Since I have already all the clocks I need, can I successfully constrain this design without using PLLs? It is necessary to declare multicycle paths? If so, why?
P.S. I am still willing to read more about the topic, therefore, if you know any uncommonly clear text about timing constraints, please share it too :)