# MOSFET channel length modulation - Glossing over physics

I am having trouble understanding an aspect of the channel length modulation/pinch off of MOSFETs.

My current understanding (For NMOS) is that when a positive voltage is applied to the gate, the P-doped regions majority carriers, holes, are repelled from the gate (Electrons are attracted to the opposite charge and fill the holes), leaving negative ions in a channel for the current to flow across. No PN junction, no problem. Current flows fine.

So when my professor tells us that if we increase the drain voltage, the channel will narrow and eventually pinch off at one end, I think it makes perfect sense. Of course! The increased voltage will move the center of attraction closer to the drain, causing the electrons to be attracted towards the drain and away from the source, so the channel will be narrower at the source and eventually pinch off when the drain has pulled all of the electrons that should have gone near the source closer to the drain.

However, to the professor, it works the opposite way. The channel pinches off near the drain. I can't conceive why adding positive voltage would cause electrons to be less attracted to you. I have asked classmates and the professor and nobody seems to have any idea. Classmates say it doesn't matter, the professor says that what matters is the difference in voltage, not the actual voltage. I found This Youtube Video where at 3:00 he says that the "Positivity" between 0.2V and 0.5V is 0.3V. What on earth is positivity? Why take the difference instead of the sum?

• WARNING: pinchoff doesn't mean "pinch closed." During pinchoff the channel is narrow, filled with mobile carriers, and the FET starts acting like a current source. But without pinchoff the channel becomes extremely wide, and the FET acts like a variable resistor. Amplifiers normally operate in pinchoff-mode. (And, "pinched closed" is called cutoff.) Commented Dec 7, 2017 at 10:26

Remember, the drain contact is a reverse-biased P-N junction. There is a depletion region surrounding it that gets thicker with increasing reverse bias (increasing drain voltage).

This depletion region extends into the channel, and the electric field associated with it modifies the electric field being produced by the potential difference between the gate and the substrate, making it more difficult to achieve the inversion required to create the channel at that end. This is called "pinch-off" when it completely negates the inversion, creating a gap in the channel.

This paper: MOSFET Device Physics and Operation contains a lot of the mathematical detail along with some nice diagrams.

• Exactly what I was looking for. My only question now is why my professors were so totally unable to explain what now seems to be a fairly simple concept. Commented Dec 7, 2017 at 1:52
1. FET Physics link Lots of math.. remember original FETs were Depletion Mode and Vgs is opposite to Enhance Mode , most efficient and common today.

## Bonus details

1. What matters to designers for using Nch-enh is how the charge current changes as it begins to transition the conduction state.
2. The gate charge goes up as the Drain-Source resistance RdsOn goes down when the Vgs ~ Vgs(th).
3. Threshold only defines the start of conduction between Drain and Source while gate charge rises and demands low gate resistance to drive this charge switch quickly. dVgs/dt=Ig/Ciss
4. After switching Vgs and Vds, the gate current drops towards 0 and RdsOn conducts according to the Vgs vs RdsOn value curve.

5. FETs are defined by many specs. Of importance to switching is the differential Vgs voltage threshold to Drain-Source conduction. This is just the threshold, not the voltage needed for low resistance switch.

6. When a channel conducts with a narrow gap it's capacitance rises sharply. This means the gate current spikes sharply during this transition until it becomes a low resistance switch. So external gate drive resistance tends to be about 100 to 1000x the output RdsOn and may match the gate input incremental resistance or higher if less than optimal slew rate is desirable to reduce EMI.

7. C=Q/V is inversely related to the RdsOn [Ohms] are always rated at some standard Vgs and Vds. See Coulomb's law to see how channel gap and capacitance are related.

8. Pch are just the complementary and like PNP, must be slightly larger to match the conduction resistance, Rce for a BJT or RdsOn of NFET to become matched as they are in most CMOS logic drivers.
9. 5V logic IC's like 74HCxxx tend to be RdsOn = 50 ~ 60 Ohms +/-25% or more at T extremes
10. 3.3 max logic IC's tend to be ~ 25 Ohms to switch faster at lower voltage

Note from datasheets that Vgs ( rated RdsOn)= 2x to 3x Vgs(th) threshold where it starts conduction at a fairly high resistance. Then as Vgs increases beyond this RdsOn only reduces slightly and Gate current drops to near 0.

more details;

Coulomb's Law

Gate capacitance vs. Gate charge in n-ch FETs, and how to calculate power dissipation during charging/discharging of the gate

• This area is reserved for answers to the question at the top of the page. This does not in any way address the actual question relating to pinch-off and channel length modulation. To request clarification or critique a post, leave a comment below it. Commented Dec 7, 2017 at 1:20
• I had a link "If it is advanced math or highly technical, give me a reference with which to self-educate" Feel free to provide a better answer Dave. Commented Dec 7, 2017 at 1:21
• Indeed, and I meant that. It is morbidly hilarious to me just how little we are taught in ECE college. None of what you posted makes any sense to me, but I accept responsibility for my education. Hopefully I can make some sense of this after some more research. Thanks for the answer regardless. Commented Dec 7, 2017 at 1:30