There are tolerances involved but < Td/2 is possible to get ignored.
We have variables for rise time, threshold, propagation delay and setup time for setting the latch after 2 gate delays. Each of these variables affects the result. But if the total delay to setup a permanent positive feedback latch is greater than the input pulse duration, then no action occurs and it would appear as internal glitch just below the threshold where the gate cannot switch the output with a load capacitance and dynamically changing source resistance.
This is what happens since all insulation has capacitance between conductors.
I am not ashamed to say that in the late 70's when I had a race condition on complex system, I added a small 1nF cap to "swallow" the pulse current due to extreme time constraints. But I would not promote this as a design ideal solution. It is better to re-synchronize signals to prevent glitches from asynchronous propagation delays.
It is also how I used to create very narrow one shots using a small propagation delay to just exceed the Tpd of the XOR gate and thus with two inputs the output is a result of the Tpd plus any differences in RdsOn that produces asymmetric rise/fall times and prop delays.
simulate this circuit – Schematic created using CircuitLab