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In an exercise I got an example circuit

example circuit

For one question, there is \$S(t_0)=1\$ for just \$T/3\$ (third of propagation delay [confusingly called transmission delay here] of every gate in circuit). For my understanding, there would actually nothing happen to Q' or even Q, since the signal is already gone when the NOR gate is 'ready'. Am I wrong here? What happens to an impulse shorter than the propagation delay? Is it swallowed? or is \$Q'(t_0+T)=0\$ for \$T/3\$?

I'd be thankful for any hints or a direction...

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    \$\begingroup\$ Ok, maybe there's an issue with translation. The exercise gives just that picture and says that any gate in that circuit has a 'transmission delay' (wikipedia translation) although T is used for propagation delay in the script of the course. \$\endgroup\$ – Andreas H. Dec 12 '17 at 22:18
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There are tolerances involved but < Td/2 is possible to get ignored.

We have variables for rise time, threshold, propagation delay and setup time for setting the latch after 2 gate delays. Each of these variables affects the result. But if the total delay to setup a permanent positive feedback latch is greater than the input pulse duration, then no action occurs and it would appear as internal glitch just below the threshold where the gate cannot switch the output with a load capacitance and dynamically changing source resistance.

other info

This is what happens since all insulation has capacitance between conductors.

I am not ashamed to say that in the late 70's when I had a race condition on complex system, I added a small 1nF cap to "swallow" the pulse current due to extreme time constraints. But I would not promote this as a design ideal solution. It is better to re-synchronize signals to prevent glitches from asynchronous propagation delays.

It is also how I used to create very narrow one shots using a small propagation delay to just exceed the Tpd of the XOR gate and thus with two inputs the output is a result of the Tpd plus any differences in RdsOn that produces asymmetric rise/fall times and prop delays.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Thanks for the extensive explanation. The example is just an academical one, hence there are no detailed variables (rise time, setup etc), just that variable T, that he (professor) calls transmission delay (meaning propagation delay, deriving from his lecture notes). So if I get you right, a T/3 impuls would result in a glitch, at max, right? I mean, for academical calculation, not in electronic practice. \$\endgroup\$ – Andreas H. Dec 13 '17 at 9:33

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