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I am using Vivado (2017.4) and have been trying to experiment with the Clocking Wizard IP. I understand how to create a new IP but am not sure what to do with the HDL file it generates. I've looked at a lot of tutorials and they all seem to have different methods for incorporating the new clock speed into their project.

Does anyone know of a standard way to use the code generated by the Clocking Wizard in your project? I'm familiar with both Verilog and VHDL so any advice would be helpful!

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In the HDL file generated for the clocking wizard, you would see the entity declaration for the wizard.

For example:

entity clk_wiz_0
     port (
      clk_in1 : in std_logic,
      clk_out1: out std_logic
     );
end clk_wiz_0;

So, in your code, you can instantiate the clocking wizard as a component.

Example:

component clk_wiz_0
     port map (
      clk_in1 => your_input_clk_signal,
      clk_out1 => your_output_clk_signal
     );
end component;

While this is one method, you can also instantiate the IP in a block diagram and connect the input/output signals of your wizard in the block diagram itself. Once that is done, you can let Vivado generate the output products (VHDL/Verilog files for the block diagram) and create the wrapper/top level file for you.

Hope this helps

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There is usually just one top level module that will have pins like clock in, clock out, reset, etc. Just instantiate this in your code somewhere and connect the inputs and outputs appropriately. Check the IP core manual for a description of the pins. There may also be an instantiation template that you can just copy and paste.

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