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For an application I need to FM modulate a signal with a 10 MHz bandwidth. Due to constraints I have no control over, I have to do it in an analog way (so I can't just digitize the signal, IQ modulate, etc). The center frequency of my modulator is not of too great importance since I will have to use second converter stages to shift it up to the target band anyways.

Since no manufacturers (of which I can easily acquire ICs in low volume) seem to make FM modulators that support that bandwidth, I am looking at building my own, based on a PLL.

For the modulator, this translates to injecting the to-be-modulated signal into the error loop, after the low-pass filter of the PFD, and thus modulate the VCO. For the demodulator, we input the received signal as reference, and given the PLL loop, the PFD will try and output the wanted signal as error to the VCO (but the filter prevents it from reaching the VCO).

In the modulator case, we require that the VCO control bandwidth is high enough to actually modulate. In the demodulator, we require that the PFD has sufficient output bandwidth to keep up with this 10 MHz modulation. However, in single-chip PLLs, neither of these parameters are often specified (and I don't think they have enough bandwidth for my application, though I will have to verify this with measurements).

For this reason I am now also looking at using standalone blocks to build a fast enough PLL. Minicircuits have various oscillators with high control-voltage-bandwidth, so that just leaves me with the PFD. There are a few very fast ones on the market, but none of them give a bandwidth as they operate in a more digital manner (pulsing currents to go up or down in frequency) and list rise and fall times. For example, the ON Semi MCH12140 datasheet lists a worst-case 20-80% rise/fall time of 350 ps. How do I relate this to the bandwidth of FM demodulation I can perform using this device?

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    \$\begingroup\$ I've done what sounds like this (15 Mbps) for a carrier of 400 MHz using direct FM in a colpitts oscillator and it worked very well so maybe you might be over-complicating things. What is your carrier frequency? \$\endgroup\$ – Andy aka Jul 15 '18 at 10:10
  • \$\begingroup\$ The goal is to work in the 5.8 GHz ISM band. What I am worried about with a free-running VCO is the frequency stability and precision - my reasoning was that a PLL can allow me to get the stability and precision of a fixed crystal oscillator. \$\endgroup\$ – Joren Vaes Jul 15 '18 at 11:06
  • \$\begingroup\$ If your signal BW DC to 10MHz and channel BW is say 20MHz shouldn’t you be using multi-phase amplitude modulation with symbol compression, error correction etc not FM. or one of the more common . With this low deviation ratio your CNR to SNR gain is low and sensitivity to passband group delay distortion is much greater. \$\endgroup\$ – Sunnyskyguy EE75 Jul 15 '18 at 13:01
  • \$\begingroup\$ @TonyEErocketscientist, I should, but I can't. I have to build a system that is backwards compatible with single chip TX/RX solutions that use FM modulation. So while I might want to, I am unable to choose any more modern and arguably better solution to this problem. \$\endgroup\$ – Joren Vaes Jul 15 '18 at 13:04
  • \$\begingroup\$ How about RLL BW compression what are your specs in MHz/V and linearity, stability etc \$\endgroup\$ – Sunnyskyguy EE75 Jul 15 '18 at 13:10
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Do you need a PLL? What are your distortion requirements, linearity of FM deviation versus input voltage? Don't rush off down the PLL route without having first looked at direct modulation.

Start with the specifications you require for the FM signal. Linearity and noise, as well as modulation bandwidth and deviation.

It is far simpler to modulate a VCO directly, lower power, if you can tolerate any tuning law non-linearity. Different VCOs have different linearity. A wide deviation VCO can be used in a small, nearly linear, part of its tuning curve.

Even if you've tried direct modulation and found it wanting, don't give up on it without a bit of investigation. I personally have used a VCO which had a kink in its tuning bandwidth curve at about 500kHz. The main LC tank tuning went via inductors, but the gain/sustaining tuning went via an RC. The manufacturer was persuaded to modify it to use inductors both both tuning points, which increased the flat bandwidth to more than 10MHz.

A colleague of mine made a TV transmitter exciter which started with two VCOs being modulated differentially and mixed, to get a low frequency, wide deviation, high linearity, low noise, wide bandwidth FM signal.

If you do end up using a PLL, then 10MHz bandwidth is fairly straightforward. You could use a digital phase detector. They don't quote a bandwidth, because it's as wide as permitted by the input rates, and limited by what you do with it afterwards. However, for wide bandwidths like 10MHz, I'd tend to use an analogue phase detector, an RF mixer with a DC-coupled IF. It's no faster, but is quieter and better behaved.

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  • \$\begingroup\$ Thanks, you have given me some food for thought. My reasoning behind the PLL is that this gives me the stability and precision of a crystal oscillator, as I would like my design to require no tuning or calibration (I should have mentioned this in the original question, my bad). \$\endgroup\$ – Joren Vaes Jul 15 '18 at 11:08
  • \$\begingroup\$ injecting the to-be-modulated signal into the error loop, after the low-pass filter of the PFD, and thus modulate the VCO You'll still be subject to analogue errors, a PLL run like that is not a synthesiser. You can build a synthesiser stabilised modulator, you can modulate a synthesiser. It depends on the bandwidth of the signal you're modulating. I patented a method of running a synthesiser with dc-coupled FM modulation if you're interested. \$\endgroup\$ – Neil_UK Jul 15 '18 at 12:46
  • \$\begingroup\$ @Niel_UK, but with a PLL, you can use a slow loop to fix your center frequency with a high quality reference (eg. xtal), and thus not have to deal with tuning or calibration of the center frequency of your oscillator. I don't quite understand what else you would mean with "subject to analogue errors", unless I am misunderstanding the theory of PLLs (which is entirely possible as I am new to designing them) \$\endgroup\$ – Joren Vaes Jul 15 '18 at 12:57
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    \$\begingroup\$ What's carried by the modulation? What's the minimum frequency for AC coupling? \$\endgroup\$ – Neil_UK Jul 15 '18 at 13:22
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    \$\begingroup\$ One reason the LF modulation requirement is important is that if you're just synthesising the centre frequency and using single point modulation, then the phase modulation is going to be present at your PSD. Normally we'd use a large prescaler to drop the frequency, and so also the LF phase modulation, so that it's less than half a cycle. The lower the modulation frequency you want to come down to, the larger is the phase modulation. You need the modulation fully specified before you can design your synthesiser. \$\endgroup\$ – Neil_UK Jul 15 '18 at 13:55
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Depending on what data-eye your existing receivers need, and the Signal Noise Ratio, and Local Oscillator phasenoise (contributes to SNR in IF and in Demod), you may be able to simply use a square wave drive into some varactor-tuned oscillator. The question becomes, if modulation is always present, how to set the Center Frequency.

At this point in your thinking, with the existing system performance not yet characterized, topologies cannot be clearly chosen.

Regarding bandwidth of PFD, this ONNN Semi FF has 350 pS Tpd

https://www.onsemi.com/pub/Collateral/NB4L52-D.PDF

and I'd be comfortable using 2 of them in the classic PFD approach, with some 2-input gate to determine when both Up and Down outputs have become active. That gate output drives some small delay to ensure a full output swing of the Up and Down pulses; the delayed signal resets both of the FFs.

Assuming 350 pS FF delay, 200 pS gate delay, 200 pS "allow for full swing" delay, and 200 pS reset-the-FFs time, and 100 pS "recover from Reset", the total cycle time is 350 + 200 + 200 + 200 + 100 = 1,050 pS, or 950MHz.

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