Understanding PLL performance: PFD output bandwidth

Question

For an application I need to FM modulate a signal with a 10 MHz bandwidth. Due to constraints I have no control over, I have to do it in an analog way (so I can't just digitize the signal, IQ modulate, etc). The center frequency of my modulator is not of too great importance since I will have to use second converter stages to shift it up to the target band anyways.

Since no manufacturers (of which I can easily acquire ICs in low volume) seem to make FM modulators that support that bandwidth, I am looking at building my own, based on a PLL.

For the modulator, this translates to injecting the to-be-modulated signal into the error loop, after the low-pass filter of the PFD, and thus modulate the VCO. For the demodulator, we input the received signal as reference, and given the PLL loop, the PFD will try and output the wanted signal as error to the VCO (but the filter prevents it from reaching the VCO).

In the modulator case, we require that the VCO control bandwidth is high enough to actually modulate. In the demodulator, we require that the PFD has sufficient output bandwidth to keep up with this 10 MHz modulation. However, in single-chip PLLs, neither of these parameters are often specified (and I don't think they have enough bandwidth for my application, though I will have to verify this with measurements).

For this reason I am now also looking at using standalone blocks to build a fast enough PLL. Minicircuits have various oscillators with high control-voltage-bandwidth, so that just leaves me with the PFD. There are a few very fast ones on the market, but none of them give a bandwidth as they operate in a more digital manner (pulsing currents to go up or down in frequency) and list rise and fall times. For example, the ON Semi MCH12140 datasheet lists a worst-case 20-80% rise/fall time of 350 ps. How do I relate this to the bandwidth of FM demodulation I can perform using this device?

Answer 1

Do you need a PLL? What are your distortion requirements, linearity of FM deviation versus input voltage? Don't rush off down the PLL route without having first looked at direct modulation.

Start with the specifications you require for the FM signal. Linearity and noise, as well as modulation bandwidth and deviation.

It is far simpler to modulate a VCO directly, lower power, if you can tolerate any tuning law non-linearity. Different VCOs have different linearity. A wide deviation VCO can be used in a small, nearly linear, part of its tuning curve.

Even if you've tried direct modulation and found it wanting, don't give up on it without a bit of investigation. I personally have used a VCO which had a kink in its tuning bandwidth curve at about 500kHz. The main LC tank tuning went via inductors, but the gain/sustaining tuning went via an RC. The manufacturer was persuaded to modify it to use inductors both both tuning points, which increased the flat bandwidth to more than 10MHz.

A colleague of mine made a TV transmitter exciter which started with two VCOs being modulated differentially and mixed, to get a low frequency, wide deviation, high linearity, low noise, wide bandwidth FM signal.

If you do end up using a PLL, then 10MHz bandwidth is fairly straightforward. You could use a digital phase detector. They don't quote a bandwidth, because it's as wide as permitted by the input rates, and limited by what you do with it afterwards. However, for wide bandwidths like 10MHz, I'd tend to use an analogue phase detector, an RF mixer with a DC-coupled IF. It's no faster, but is quieter and better behaved.

Answer 2

Depending on what data-eye your existing receivers need, and the Signal Noise Ratio, and Local Oscillator phasenoise (contributes to SNR in IF and in Demod), you may be able to simply use a square wave drive into some varactor-tuned oscillator. The question becomes, if modulation is always present, how to set the Center Frequency.

At this point in your thinking, with the existing system performance not yet characterized, topologies cannot be clearly chosen.

Regarding bandwidth of PFD, this ONNN Semi FF has 350 pS Tpd

https://www.onsemi.com/pub/Collateral/NB4L52-D.PDF

and I'd be comfortable using 2 of them in the classic PFD approach, with some 2-input gate to determine when both Up and Down outputs have become active. That gate output drives some small delay to ensure a full output swing of the Up and Down pulses; the delayed signal resets both of the FFs.

Assuming 350 pS FF delay, 200 pS gate delay, 200 pS "allow for full swing" delay, and 200 pS reset-the-FFs time, and 100 pS "recover from Reset", the total cycle time is 350 + 200 + 200 + 200 + 100 = 1,050 pS, or 950MHz.