I am going to work with a PLL and a VCO.
I have read and understood the basic procedure in which the charge pump works. I understood that say, when the reference signal (or the divided signal) is up and the VCO (divided by N) is down, the charge pump is up. When both are up or both are down, it is as it is. If the VCO is up, reference is down, the charge pump is down.
The charge pump pumps up and down like a square wave. When the reference frequency is relatively high, the CP spends more time in the high state, when the VCO frequency is relatively high, the CP spends more time in the down state.
When the reference and the VCO are almost equal in frequency, with a slight difference in phase, the CP keeps moving up and down at the same frequency as that of the reference and the VCO.
We use the loop filter to filter out frequencies higher than that of the reference and the VCO to keep the operation stable (I am stating as I understand the things.)
Where does this higher frequency come from? I thought the highest frequency of the charge pump should have been the reference frequency (the PFD frequency,) since when the reference and the VCO have a frequency difference, the charge pump stays in a single state for a longer time without shifting states, and when the frequency difference reduces, the charge pump shifts states more frequently and the maximum possible frequency, as I understand, is the PFD frequency, or the reference frequency.
Where does the higher frequency come from? How high can the frequency be? I am willing to use a PFD of 1 MHz. Would the higher frequencies be something like 2 MHz, 3 MHz, 4 MHz and so on, or would they be very high like in the hundreds? I need to understand this as I am planning to used 1206 capacitors instead of 0603, and 1206 has a worse frequency performance. The resistors I will use are not special high frequency ones. If the high frequencies are very high, I fear the filter operation being messed up.
I intend to use an ADF4106 PLL with a ~570 MHz VCO at a PFD of 1 MHz.