How does a PLL PFD produce a high frequency?

Question

I am going to work with a PLL and a VCO.

I have read and understood the basic procedure in which the charge pump works. I understood that say, when the reference signal (or the divided signal) is up and the VCO (divided by N) is down, the charge pump is up. When both are up or both are down, it is as it is. If the VCO is up, reference is down, the charge pump is down.

The charge pump pumps up and down like a square wave. When the reference frequency is relatively high, the CP spends more time in the high state, when the VCO frequency is relatively high, the CP spends more time in the down state.

When the reference and the VCO are almost equal in frequency, with a slight difference in phase, the CP keeps moving up and down at the same frequency as that of the reference and the VCO.

We use the loop filter to filter out frequencies higher than that of the reference and the VCO to keep the operation stable (I am stating as I understand the things.)

Where does this higher frequency come from? I thought the highest frequency of the charge pump should have been the reference frequency (the PFD frequency,) since when the reference and the VCO have a frequency difference, the charge pump stays in a single state for a longer time without shifting states, and when the frequency difference reduces, the charge pump shifts states more frequently and the maximum possible frequency, as I understand, is the PFD frequency, or the reference frequency.

Where does the higher frequency come from? How high can the frequency be? I am willing to use a PFD of 1 MHz. Would the higher frequencies be something like 2 MHz, 3 MHz, 4 MHz and so on, or would they be very high like in the hundreds? I need to understand this as I am planning to used 1206 capacitors instead of 0603, and 1206 has a worse frequency performance. The resistors I will use are not special high frequency ones. If the high frequencies are very high, I fear the filter operation being messed up.

I intend to use an ADF4106 PLL with a ~570 MHz VCO at a PFD of 1 MHz.

Answer 1

The PLL's loop filter doesn't filter out frequencies above the reference frequency, it filters out the reference frequency (and its harmonics). If you have a 1MHz reference, you'd design the loop filter to attenuate a lot at 1MHz already. Depending on the desired tracking speed of the PLL, you might go for a -3dB corner frequency of 100kHz or so for the (at least 2nd order) loop filter.

The PFD's output signal is binary, it's just more positive or more negative on average depending on the phase/frequency relationship of the reference and (divided) output signals. You have to integrate (low-pass filter) this signal to get the VCO control voltage. The ADF4106's charge pump, coupled with the external integration capacitors and low-pass filter, achieves this goal. The charge pump is part of the loop filter; its purpose is to create an integrator, which also acts as a low-pass filter.

If the loop filter didn't filter out the reference frequency, the VCO's control voltage would fluctuate a lot at that frequency. This means that the PLL's output frequency would change over the course of a single period of the reference signal, effectively frequency modulating it. This is very much undesirable, which is why you might even want to put a notch in your loop filter at the reference frequency. Of course, you have to make sure that the system's overall feedback loop remains stable (it must have enough phase margin).

This is also why PLLs in microprocessors often take a long time (milliseconds) to lock. They're optimized for frequency stability so their loop filter has a low corner frequency to attenuate the reference frequency a lot and thereby reduce jitter.

TL;DR: No, there are no high frequencies in the loop filter circuit other than the reference frequency and its harmonics (which are all heavily attenuated).