Error with Assert statement in Verilog

Question

I have the following assert statement in a for loop, which is within a generate block:

34   assert ((a[j] == 1'b1) || (a[j] == 1'b0))
35   else $error("Input 'a[" + j + "]' is not a digital logic value");

When I try to compile, I get the following error:

Error: file(34): near "(": syntax error, unexpected '(', expecting property

From what I can see, I'm not missing any parentheses in the

Answer 1

It isn't telling you that you're missing any parentheses; it's telling you that it isn't expecting a parenthesis at all in that spot.

You didn't provide any context, but if your assert is outside a procedural block (initial or always), then a property name must appear between the assert and the (. This is known as an "concurrent assert".

The other type (the syntax you used) is an "immediate assert", and can only appear inside a procedural block.

Additional details here.