Error with Assert statement in Verilog

I have the following assert statement in a for loop, which is within a generate block:

34   assert ((a[j] == 1'b1) || (a[j] == 1'b0))
35   else \$error("Input 'a[" + j + "]' is not a digital logic value");


When I try to compile, I get the following error:

Error: file(34): near "(": syntax error, unexpected '(', expecting property

From what I can see, I'm not missing any parentheses in the

You didn't provide any context, but if your assert is outside a procedural block (initial or always), then a property name must appear between the assert and the (. This is known as an "concurrent assert".