I2C data sampling is done at clock edge or level

Question

I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication.

One thing that I could not understand is related to the sampling of the data at the SDA line. Is it done at the falling or rising edge of the SCL line or is it done at the SCL HIGH or LOW level?

Answer 1

Data transfer-

The state of SDA(high or low) can change only when SCL is low. This means SDA must be stable when SCL high.

Sampling is done while the SCL going 0 to 1 state. Changing SDA when SCL is low provides some timing margin for accurate sampling.

As for I2C itself is a mutual interface standard. Both sides(TX and RX) can control the SDA line in different times. So SDA pins on both sides must be birectional.

Start and Stop Conditions-

Start: when SCL:HIGH , Falling edge of SDA occurs

Stop: when SCL: HIGH , Rising edge of SDA occurs

Answer 2

The I2C interface is a de facto standard that is now controlled by NXP. Search for the NXP "I2C-bus specification and user manual", UM10204.

The standard specifies a data bit setup time before the rising edge of the clock and a data hold time after the falling edge of the clock, so a receiver could potentially use either edge of the clock, or could use a level-sensitive latch when the clock is high.

Of course, the receiver must also be able to detect the start and stop conditions where the SDA line changes while the SCL line is high.

Answer 3

From my answer from a similar question...

To be a bit more precise, the data isn't just sampled at the rising edge, but must change before the rising edge and be stable for the entire HIGH period of the SCL.

This screenshot was taken directly from the I2C Specification.

Note: The ACK bit must follow this as well:

More about timing

After reading your comments on your question you seem to be curious about whether there should be a delay after you change your SDA before you change your SCL. The answer is yes, but it's all dependent on what mode your device will operate in. See tables 9 and 10 of the specification. Table 10 specifically refers to the timings, which may be what you're interested in.

For some very basic numbers, here are the min and max for Standard-mode for data setup and hold (min in left, max in right):

If you notice, the data hold time has 0, but there is a caveat:

This is simply restating what you see on the last row of the above picture, the maximum fall time of the SCL or SDA lines in Standard-mode must be under 300 ns, therefore the data hold time should be at least 300 ns to account for the slowest possible SCL transition.

In Standard-mode, V_IHmin (the minimum input voltage to be considered high) is 0.7V. V_ILmax (the maximum input voltage to be considered low) is 0.3V. That means the range between 0.3V and 0.7V is unstable.

What all this means

Assuming you are operating in Standard-mode:

• SDA must be setup (moved to a stable range) 250ns before SCL goes high.
• SDA must be stable for the entire HIGH period of SCL.
• SDA must be held for 300ns while SCL goes low.

Saying "while" here seems a bit strange, but it's to emphasize the 0 + 300ns minimum needed for SCL transition back to low. Typically I believe the hold time will be (1/2*SCL_period) + 300ns. More information can be found in Table 10 of the specification to understand what operating mode you are dealing with.