I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication.

One thing that I could not understand is related to the sampling of the data at the SDA line. Is it done at the falling or rising edge of the SCL line or is it done at the SCL HIGH or LOW level?

  • \$\begingroup\$ For I2C is this data sampling edges requirements is part of the I2C protocol or not? Is it done on both edges? \$\endgroup\$ – alt-rose Nov 18 '19 at 8:00
  • 1
    \$\begingroup\$ There are a number of different modes for I2C communication. Some list sampling at the falling edge, while some say the rising edge is an option. Best to refer to the wiki page for all the different I2C modes and specifications related to clock edges, see: en.wikipedia.org/wiki/I%C2%B2C \$\endgroup\$ – Nedd Nov 18 '19 at 8:11

Data transfer-

The state of SDA(high or low) can change only when SCL is low. This means SDA must be stable when SCL high.

Sampling is done while the SCL going 0 to 1 state. Changing SDA when SCL is low provides some timing margin for accurate sampling.
enter image description here

As for I2C itself is a mutual interface standard. Both sides(TX and RX) can control the SDA line in different times. So SDA pins on both sides must be birectional.

Start and Stop Conditions-

Start: when SCL:HIGH , Falling edge of SDA occurs

Stop: when SCL: HIGH , Rising edge of SDA occurs

  • \$\begingroup\$ Your last sentence contradicts the first sentence. \$\endgroup\$ – Elliot Alderson Nov 18 '19 at 12:41
  • \$\begingroup\$ I think everyone understands(including you) that the last sentence means start and stop commands and the first sentence means data bits. Something strange even though you said the same thing. \$\endgroup\$ – Berker Işık Nov 18 '19 at 14:04

The I2C interface is a de facto standard that is now controlled by NXP. Search for the NXP "I2C-bus specification and user manual", UM10204.

The standard specifies a data bit setup time before the rising edge of the clock and a data hold time after the falling edge of the clock, so a receiver could potentially use either edge of the clock, or could use a level-sensitive latch when the clock is high.

Of course, the receiver must also be able to detect the start and stop conditions where the SDA line changes while the SCL line is high.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.